; [ CLKDIV_VAL>1 ; 意思是 Fclk:Hclk 不是 1:1.
; bl MMU_SetAsyncBusMode
; |
; bl MMU_SetFastBusMode ; default value.
; ] ; ==手册第243页==
; If HDIVN is not 0, the CPU bus mode has to be changed from the fast bus mode to the asynchronous
; bus mode using following instructions
;MMU_SetAsyncBusMode
;mrc p15,0,r0,c1,c0,0
;orr r0,r0,#R1_nF:OR:R1_iA
;mcr p15,0,r0,c1,c0,0
[ CLKDIV_VAL>1 ; 意思是 Fclk:Hclk 不是 1:1.
mrc p15,0,r0,c1,c0,0
orr r0,r0,#0xc0000000;R1_nF:OR:R1_iA
mcr p15,0,r0,c1,c0,0
|
mrc p15,0,r0,c1,c0,0
bic r0,r0,#0xc0000000;R1_iA:OR:R1_nF
mcr p15,0,r0,c1,c0,0
]
;配置 UPLL
;//Configure UPLL Fin=12.0MHz UFout=48MHz
ldr r0,=UPLLCON
ldr r1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV) ;//USB PLL CONFIG 56,2,2===>48MHz
str r1,[r0]
;7个nop必不可少！！
nop ;// Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting
nop
;hardware be completed.
nop
nop
nop
nop
nop
;配置 MPLL
;//Configure MPLL Fin=12.0MHz MFout=304.8MHz
ldr r0,=MPLLCON
ldr r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV) ;68,1,1 ==>304MHz
str r1,[r0]
]
;检查是否从SLEEP模式中恢复
;//Check if the boot is caused by the wake-up from SLEEP mode.
ldr r1,=GSTATUS2
ldr r0,[r1]
tst r0,#0x2 ;test if bit[1] is 1 or 0 0->C=1
; 1->C=0
;In case of the wake-up from SLEEP mode, go to SLEEP_WAKEUP handler.
bne WAKEUP_SLEEP ;C=0,jump EXPORT StartPointAfterSleepWakeUp
StartPointAfterSleepWakeUp ;=============================================================================== | 
