ARM - STM32 使用11.0592MHz晶振（3） selected, factor

• #else
  
•       pllmull = pllmull >> 18;  
• 
  
•       if (pllmull != 0x0D)  
•       {  
•          pllmull += 2;  
•       }  
•       else
  
•       { /* PLL multiplication factor = PLL input clock * 6.5 */
  
•         pllmull = 13 / 2;   
•       }  
• 
  
•       if (pllsource == 0x00)  
•       {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
  
•         RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;  
•       }  
•       else
  
•       {/* PREDIV1 selected as PLL clock entry */
  
• 
  
•         /* Get PREDIV1 clock source and division factor */
  
•         prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;  
•         prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;  
• 
  
•         if (prediv1source == 0)  
•         { /* HSE oscillator clock selected as PREDIV1 clock entry */
  
•           RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;            
•         }  
•         else
  
•         {/* PLL2 clock selected as PREDIV1 clock entry */
  
• 
  
•           /* Get PREDIV2 division factor and PLL2 multiplication factor */
  
•           prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;  
•           pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2;   
•           RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                           
•         }  
•       }  
• #endif /* STM32F10X_CL */
  
•       break;  
• 
  
•     default:  
•       RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;  
•       break;  
•   }  
• 
  
•   /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
  
•   /* Get HCLK prescaler */
  
•   tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;  
•   tmp = tmp >> 4;  
•   presc = APBAHBPrescTable[tmp];  
•   /* HCLK clock frequency */
  
•   RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;  
•   /* Get PCLK1 prescaler */
  
•   tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;  
•   tmp = tmp >> 8;  
•   presc = APBAHBPrescTable[tmp];  
•   /* PCLK1 clock frequency */
  
•   RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;  
•   /* Get PCLK2 prescaler */
  
•   tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;  
•   tmp = tmp >> 11;  
•   presc = APBAHBPrescTable[tmp];  
•   /* PCLK2 clock frequency */
  
•   RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;  
•   /* Get ADCCLK prescaler */
  
•   tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;  
•   tmp = tmp >> 14;  
•   presc = ADCPrescTable[tmp];  
•   /* ADCCLK clock frequency */
  
•   RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;  
• }