PLL_BASE
Xilinx的低端的FPGA中都用DCM,高级一点的都用PLL.
这个再多说一句,使用PLL时,输出时钟
Clk_out = Clkin*Mult / DIVCLK_DIVIDE /CLKOUTx_DIVIDE;
Eg.
PLL_BASE #(
.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
.CLKFBOUT_MULT(2), // Multiplication factor for all output clocks
.CLKFBOUT_PHASE(0.0), // Phase shift (degrees) of all output clocks
.CLKIN_PERIOD(0.000), // Clock period (ns) of input clock on CLKIN
.CLKOUT0_DIVIDE(5), // Division factor for CLKOUT0 (1 to 128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.01 to 0.99)
.CLKOUT0_PHASE(0.0), // Phase shift (degrees) for CLKOUT0 (0.0 to 360.0)
.CLKOUT1_DIVIDE(1), // Division factor for CLKOUT1 (1 to 128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT1 (0.01 to 0.99)
.CLKOUT1_PHASE(0.0), // Phase shift (degrees) for CLKOUT1 (0.0 to 360.0)
.CLKOUT2_DIVIDE(1), // Division factor for CLKOUT2 (1 to 128)
.CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT2 (0.01 to 0.99)
.CLKOUT2_PHASE(90), // Phase shift (degrees) for CLKOUT2 (0.0 to 360.0)
.CLKOUT3_DIVIDE(2), // Division factor for CLKOUT3 (1 to 128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT3 (0.01 to 0.99)
.CLKOUT3_PHASE(0.0), // Phase shift (degrees) for CLKOUT3 (0.0 to 360.0)
.CLKOUT4_DIVIDE(1), // Division factor for CLKOUT4 (1 to 128)
.CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT4 (0.01 to 0.99)
.CLKOUT4_PHASE(0.0), // Phase shift (degrees) for CLKOUT4 (0.0 to 360.0)
.CLKOUT5_DIVIDE(1), // Division factor for CLKOUT5 (1 to 128)
.CLKOUT5_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT5 (0.01 to 0.99)
.CLKOUT5_PHASE(0.0), // Phase shift (degrees) for CLKOUT5 (0.0 to 360.0)
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS",
// "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL",
// "DCM2PLL", "PLL2DCM"
.DIVCLK_DIVIDE(1), // Division factor for all clocks (1 to 52)
.REF_JITTER(0.100) // Input reference jitter (0.000 to 0.999 UI%)
) pll2 (
.CLKFBOUT(CLKFBIN), // General output feedback signal
.CLKOUT0(clk_100M), // 80M 0d
.CLKOUT1(), // 10M 0d
.CLKOUT2(), //80M 90d
.CLKOUT3(), // One of six general clock output signals
.CLKOUT4(), // One of six general clock output signals
.CLKOUT5(), // One of six general clock output signals
.LOCKED(), // Active high PLL lock signal
.CLKFBIN(CLKFBIN), // Clock feedback input
.CLKIN(clk), // Clock input
.RST(~rst_n) // Asynchronous PLL reset
);
再举IO组件为例,
I/O 组件提供了本地时钟缓存、标准单端I/O 缓存、差分I/O 信号缓存、DDR 专用I/O 信号缓存、可变抽头延迟链、上拉、下拉以及单端信号和差分信号 之间的相互转换，具体包括了21 个原语.
BUFIO
上文讲过
IBUFDS
用于将差分输入信号转为标准单端信号,且可加入可选延迟.
输入信号为I,IB,一个为主,一个为从,二者相伴相反.真值表如下:
其中-*, 表示维持原输出值.
Eg. IBUFDS refclk_ibuf (.O(sys_clk_c), .I(sys_clk_p), .IB(sys_clk_n)); //差分时钟进来 |
