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- UID
- 524789
- 性别
- 男
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各位大虾，小弟有一问题求教。
使用Virtex II DCM将10M时钟倍频为64M输出。器件用的是 XC2V80-144c
在Virtex II 的文档中标明了，Virtex II的DCM模块有低速和高速两种模式，低频模式下可以实现10M到64M到倍频：使用 clkfx输出，则clkin范围为1M～210M，输出clkfx为24～210M。
分别使用ISE7.1 ISE9.2 ISE10.2 三个版本的开发环境，生成DCM模块，通过；
将DCM例化到主程序中，编译及综合通过；
使用modelsim进行功能仿真、时序仿真均通过，可以倍频到64M。
下载到芯片中后，可以输出64M，但大程序修改若干次后，芯片突然出现输入10M输出还是10M的问题。
重新做一个工程，仅加入该DCM模块，用modelsim仿真没问题，可以倍频到64M，但芯片输出结果不变，仍然是输入10M输出还是10M。
怀疑芯片出问题，用新的芯片重新焊接一块板，问题依旧；
将输入信号增加到50M，进入文档中所说的高频模式（输入大于等于50M），可以实现倍频(从50M->60M)、分频，但一旦进入低速的频率范围，又无法倍频了。说明芯片没有问题的。
例化DCM的语句：
Clock_lock1 DCM_module (
.CLKIN_IN(clk),
.RST_IN(reset_in),
.CLKFX_OUT(clk_64M),
.CLKFX180_OUT(clk_64M_180),
.CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT),
.CLK0_OUT(clk0),
.LOCKED_OUT(DCM_locked)
);
生成的DCM模块对应的verilog
文件：
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / // /
// /___/ / Vendor: Xilinx
// / Version : 7.1i
// Application :
// / / Filename : Clock_lock1.v
// /___/ / Timestamp : 04/29/2008 22:00:20
// /
// ___/___
//
//Command:
//Design Name: Clock_lock1
//
// Module Clock_lock1
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module Clock_lock1(CLKIN_IN,
RST_IN,
CLKFX_OUT,
CLKFX180_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT,
LOCKED_OUT);
input CLKIN_IN;
input RST_IN;
output CLKFX_OUT;
output CLKFX180_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKFX180_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND;
assign GND = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
BUFG CLKFX180_BUFG_INST (.I(CLKFX180_BUF),
.O(CLKFX180_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
// Period Jitter (unit interval) for block DCM_INST = 0.09 UI
// Period Jitter (Peak-to-Peak) for block DCM_INST = 1.34 ns
DCM DCM_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND),
.PSCLK(GND),
.PSEN(GND),
.PSINCDEC(GND),
.RST(RST_IN),
.CLKDV(),
.CLKFX(CLKFX_BUF),
.CLKFX180(CLKFX180_BUF),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
// synthesis attribute CLK_FEEDBACK of DCM_INST is "1X"
// synthesis attribute CLKDV_DIVIDE of DCM_INST is "2.000000"
// synthesis attribute CLKFX_DIVIDE of DCM_INST is "5"
// synthesis attribute CLKFX_MULTIPLY of DCM_INST is "32"
// synthesis attribute CLKIN_DIVIDE_BY_2 of DCM_INST is "FALSE"
// synthesis attribute CLKIN_PERIOD of DCM_INST is "100.000000"
// synthesis attribute CLKOUT_PHASE_SHIFT of DCM_INST is "NONE"
// synthesis attribute DESKEW_ADJUST of DCM_INST is "SYSTEM_SYNCHRONOUS"
// synthesis attribute DFS_FREQUENCY_MODE of DCM_INST is "LOW"
// synthesis attribute DLL_FREQUENCY_MODE of DCM_INST is "LOW"
// synthesis attribute DUTY_CYCLE_CORRECTION of DCM_INST is "TRUE"
// synthesis attribute FACTORY_JF of DCM_INST is "C080"
// synthesis attribute PHASE_SHIFT of DCM_INST is "0"
// synthesis attribute STARTUP_WAIT of DCM_INST is "FALSE"
// synopsys translate_off
defparam DCM_INST.CLK_FEEDBACK = "1X";
defparam DCM_INST.CLKDV_DIVIDE = 2.000000;
defparam DCM_INST.CLKFX_DIVIDE = 5;
defparam DCM_INST.CLKFX_MULTIPLY = 32;
defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam DCM_INST.CLKIN_PERIOD = 100.000000;
defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCM_INST.FACTORY_JF = 16'hC080;
defparam DCM_INST.PHASE_SHIFT = 0;
defparam DCM_INST.STARTUP_WAIT = "FALSE";
// synopsys translate_on
endmodule
可以看到已经显示是“low”模式了
可能是需要设置什么东西才行，但没有找到，恳请各位大虾指点！！！！！ |
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