bwin�ͻ��- Spartan-3: 用于量大的消费类产品的第五代低成本FPGA解决方案- 赛灵思厂商_在线座谈

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座谈主题：Spartan-3: 用于量大的消费类产品的第五代低成本FPGA解决方案
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[问：wgjdp88]	请问spartan3与以前的spartan系列相比最大的特色是什么？内部是否可以嵌入microblaze这样的软核以及powerPC硬核？
[答：Danny]	Spartan-3 is built based on 90nm and 12 inches wafer. So the cost is much lower than previous Spartan family (80% lower cost then the other FPGA vendor with similiar gate count size can offer). Also it has build in 18*18 multiplier for high speed DSP application, 4 DCM for complicate clock control management. It is built based on previous successful Spartan experience with new additional feature which are requested by customer. Yes Microblaze (32bit microprocessor) can be implemented in Spartan-3 but hard core Power PC at this moment is on V-II Pro series only. Sparta-3 doesn"t support Power PC	[2003-6-10 10:32:10]
[问：zhang. sheng2]	我们正在使用spartan－2e，sparton－3除了价格优势还有其它方面的优越性吗？
[答：Lijinhua]	有的，Spartan-3有很多比Spartan-2E优越的特性。比如说：DCI,DCM,18Kbits BloakRAM,而且，在容量方面更是比Spartan-2E大很多（最大到74880LCs）。	[2003-6-10 10:41:39]
[问：willam _gann1]	FPGA做数字锁相环，是用软件实现锁相还是它内部有锁相核？
[答：Danny]	Spartan-3 has built in DLL (digital lock loop). With this build in DLL, customer can implement clock multiplier or divider in order to generate the frequency which customer wants. Also with this DLL, customer can control phrase shift in +/- 1/256 resolution in order to meet the design requirement. So with using Spartan-3, the DLL is come with free	[2003-6-10 10:42:09]
[问：Anoymous]	请问xilinx的fpga与altera的相比有何优缺点，价格如何？在国内容易买到吗？
[答：Hans]	XILINX是一个更好的解决方案.和CYCLONE相比,SPARTAN-3提供3.5倍的逻辑密度，2.5倍的I/O数目，6.5倍的RAM。和STRATIX相比，SPARTAN-3非常好的价格。因为SPARTAN-3采用90nm及一系列先进的工艺和设计，所以成本比竞争对手要低。在国内很方便买到，我们有两家代理商，科汇和华创。	[2003-6-10 10:45:17]
[问：zhl-home]	请问该低成本FPGA价位大约在什么范围？它在家电领域有没有发展市场？如果有的话能不能举几个应用的例子？
[答：Danny]	For volume pricing at the end of 2004 will be under $3.50 for XC3S50 and udner $20 for the XC3S1000, and under $100 for the XC3S4000 (based on 250K unit quantities)	[2003-6-10 10:45:50]
[问：maxxujun5]	如果一个设计必须分别在几片Spartan-3上实现，之间的互联数据线和控制线非常多，任意两片之间的数据线和控制线都超过300根，而且时钟频率争取能跑到60MHz左右，有无可能将并行的数据总线转成LVDS数据在FPGA之间传输，就象使用并行数据线传输一样。Spartan-3上是否集成了这样的I/O模块？
[答：Lijinhua]	可以的。比如说，你可以在一对LVDS差分对上跑480Mbps。这样，所用的IO差不多只需要80根了。不幸的是Spartan-3上并没有集成这样的硬件模块，不过，XILINX有相应的参考设计，用内部逻辑实现。	[2003-6-10 10:47:05]
[问：wiseberg]	做图象处理需要很多RAM做处理中间数据缓冲，Spartan-3是否会提供像VirtexE-M类似的具有较多RAM的型号？
[答：Hans]	SPARTAN-3目前没有计划出此类产品，如RAM不够多，可考虑XILINX的VIRTEX2-PRO系列。另外，SPARTAN-3还有专用的18x18乘法器，方便实现DSP的功能。	[2003-6-10 10:50:53]
[问：xzfang]	请问为什么说Spartan-3适合做数字电视方面的应用？请具体说明一下
[答：Danny]	Spartan-3 has a lot of build in feature which is needed by digital TV design. Such has high speed I/O transfer with low EMI (Spartna-3 offers flexible LVDS solution with vairous SERDER configuration). Also, the build in 18*18 dedicate multiplier is good for digital image processing. With the 4 build in DCM for clock control management, customer can easily hand differnet clock frequency domain. But the most important key point is : the price of Spartan-3 can be as low as ASIC solution but offer re-programmable capability in order to adapt the im-mature HDTV standard	[2003-6-10 10:52:22]
[问：semiking]	该类芯片的扇出系数多少？如要做控制系统如何扩充端口负载能力？
[答：Hans]	SPARTAN-3的I/0口驱动强度可以设置，最大驱动电流可到24MA.如还不够，可外加驱动器，如244/245等。	[2003-6-10 10:54:48]
[问：hellosp3]	Spartan-3的时钟全局网有几条？对于超出了全局网数量的时钟如何有效的约束使其满足时序要求？DLL有主从之分吗？block_ram容量多大？
[答：Lijinhua]	Spartan-3的时钟全局网有8条;对于超出了全局网数量的时钟我们可以用“USELOWSKEWLINES”和“MAXSKEW”属性来约束，从而使其满足时序要求；DCM（改进了的DLL）没有主从之分；BlockRAM的容量为18Kbits/块，最大的器件有1872K.	[2003-6-10 10:56:07]
[问：xqtang]	请问在Spartan-3中可以提供的MCU软核有多少种？
[答：Hans]	目前有两种，一是32位的MicroBlaze,另一种是8位的PicroBlaze.在XILINX的网站上有详细的介绍。	[2003-6-10 10:57:31]
[问：TI]	和Cyclone比有什么优势？
[答：Danny]	Spartan is built on 90nm, 8 layer copper and 12 inches wafer, so the cost is can be as low as 80% of the other FPGA competitor. Also the build in feature of Spartan-3 is much much more than other, 18*18 bit dedicated mulitiplier, 23 different I/O standard, support density migration (same PCB layout support differnet gate count device), CLB of Spartna-3 can implement as 16 bit shift register, and distributed RAM which no other FPGA vendor can offer equivalent solution. Huge build in Block RAM (1972K) to meet those memory intensive design demand.	[2003-6-10 10:58:12]
[问：zcluan]	该系列产品最高工作频率是多少？是否与PCI兼容？内部处理器具体是什么处理器？此处理器是硬core还是软core？
[答：Danny]	Yes. the current S-3 can support PCI 33Mhz 32bit and 33Mhz 4bits. Xilinx is working to plot the PCI IP core to meet 66Mhz clock frequency. Please visit Xilinx IP core website for IP core most update status The web site is www.xilinx.com/ipcenterSpartan has up to 104 18*18 bit dedicated mulitiplier which can be used to handle high speed DSP applicaiton.Unfortunately, there is no hard core microprocessor build in (only V-II Pro has built in Power PC). But Xilinx offer soft processor solution e.g Microblaze which can be implemented in Spartan-3. On price point of view, the MicroBlaze + Spartan 3 soluiton can be as low as USD $1.40 which is much more lower than a stand alone CPU	[2003-6-10 11:06:12]
[问：TI]	我还想问一下spartan-3和同样门数的Vertex-II有什么差别？价格是不是相差很多？
[答：Lijinhua]	有差别的。spartan-3比Vertex-II在CLB结构上有很大的区别。比如说：只让一半的Slice支持分布式RAM，去掉BUFT等。所有这些，都是在尽量少影响性能的前提下简化设计，缩小芯片尺寸，从而降低成本。价格上要比Vertex-II便宜很多。	[2003-6-10 11:06:32]
[问：dyq8]	我们的 ASIC 设计部门正在考虑对于短周期的设计更多地使用 FPGA 为客户部门提供解决方案，请对比 Spartan－III 与 ASIC 方案在应用中的优劣势。
[答：Hans]	SPARTAN-3与ASIC相比1）可以更快的完成设计；2）可灵活的修改设计，升级产品，从而可达到更长的生命周期；3）在中小量的产品应用中，有价格优势。4）采用90nm最先进的工艺，性能可与ASIC相当。	[2003-6-10 11:09:34]
[问：shantao]	如何用FPGA嵌入的18x18乘法器实现一些较复杂的算法，指令如何管理
[答：Danny]	Xilinx support ISE 5.2i has provide build in library core to support the 1818 multiplier. Customer can also design in VHDL or Verilog, which Xilinx ISE software also provide template on how to use it.Using the 1818 mulitiplier is as easy as you design with a two input "NAND" gate. If you need help, please contact Xilinx distributor for FAE assistant	[2003-6-10 11:09:48]
[问：willam _gann1]	spartan-3支持高性能dsp应用,是否指内部已集成dsp,性能如何
[答：Lijinhua]	spartan-3支持高性能dsp应用,但不是指内部已集成dsp处理器，而是指集成了专用硬件18X18比特乘法器，配合逻辑资源，你可以实现任意的DSP算法。乘法器的性能可以跑在100MHz以上。而且，借助XILINX的SystemGen你可以很方便地直接从算法到FPGA逻辑实现。	[2003-6-10 11:12:19]
[问：linming]	1、系统门的数量是否包括乘法器、RAM？２、分布RAM与块RAM有何区别？3、XC3S5000-4FG1156C、XCF16SFS48C、XCF32SFS48C何时能供货？价格？
[答：Danny]	Yes. The system gate count is include the multiplier, RAM.Distributed RAM is implemented in CLB. So CLB has dual funtion : eithe implemented as Logic usage, or distributed RAM/Shift register function.Block RAM is a build in dedicated RAM block which is used to implement large block.XC3S5000 will be availabel at 2004	[2003-6-10 11:14:29]
[问：wang jade_491RE]	你好,有的电路需要限定各个器件之间的相对位置关系,从而方便控制诸如时钟之类的信号.那么,请问,针对Spartan-3有什么好的办法？或者改种芯片已经采取了什么有效结构，加强了布线效率？谢谢！
[答：Hans]	在我们的开发软件ISE中可用floorplan来实现各功能模块间的相对定位。SPARTAN-3中有DCM,可灵活控制CLOCK.	[2003-6-10 11:17:40]
[问：lingf]	spartan-3 用现在的软件可以支持吗？我现在用的是foundation3.1
[答：Lijinhua]	不幸的是，foundation3.1不支持spartan-3的开发，你必须升级到ISE5.2i+SP3。如果你还要开发3S4000和3S5000这样的大器件，你必须在ISE5.2i+SP3上加补丁（http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=17110），或使用将要发布的ISE6.1i软件。	[2003-6-10 11:23:04]
[问：刘善宁]	功耗多大，带cpu的是哪种。
[答：Hans]	SPARTAN-3中没有带硬的CPU，但你可以选择软的CPU核，有32位的MicroBlaze和8位的PicroBlaze可供选择。在我们另一系列Virtex2-pro产品中有硬的POWERPC CPU.SPARTAN-3用1.2V供电，功耗相当低。具体数字和工作环境及设计相关。	[2003-6-10 11:24:39]
[问：lzg_hl]	Spartan-3内的PCI的IP核是否完全符合PCI标准，遵守的是PCI1.1还是PCI2.0呢？
[答：Danny]	Yes. Spartan-3 meeting all the timing requirement of PCI 33Mhz 32bit and 64bit standard. It meets PCI 2.0.Xilimx is working on PCI 66Mhz 32 and 64bit solution. Please contact Xilinx distributor for more detail and assistant	[2003-6-10 11:25:27]
[问：wiseberg]	请推荐一款适合用于Spartan-3的电源（线性稳压源或者开关电源均可）
[答：Hans]	linear technology : LT1764Micrel : MIC49150TI : TPS77601	[2003-6-10 11:27:14]
[问：lzg_hl]	请问如果要用FPGA来实现PCI控制8139和TFT液晶显示器应采用Spartan-3中的什么型号？
[答：Lijinhua]	请注意：Spartan-3不支持5V的PCI。如果你的PCI是3.3V的，可以使用Spartan-3。至于使用什么型号，这要看你的具体设计规格。	[2003-6-10 11:27:23]
[问：lzg_hl]	用什么开发工具开发Spartan-3？
[答：Danny]	Spartan-3 will be supported by ISE 5.2i (WebPack, BaseX, Foundation and Alliacne).	[2003-6-10 11:29:29]
[问：eewwu]	Sparten II 的DLL在产生0，90，180和270 度相移信号时频率的上限是什么？Spartan III呢
[答：Hans]	spartan-2 is 200Mspartan-3 is 326M	[2003-6-10 11:30:46]
[问：xiangx]	我们目前正在使用xc2s200 PQ208,请问xc3s系列同样封装的与2s管脚兼容吗?
[答：Hans]	不兼容。	[2003-6-10 11:32:46]
[问：lzg_hl]	Spartan-3的延时最大是多少？是否可预测？
[答：Lijinhua]	FPGA一般不谈“延时”这一概念，这是因为：FPGA的架构十分的灵活，组合逻辑的延时既包括LUT的延时还要包括布线的延时，而布线的延时跟你的设计实现有很大关系。至于延时预测性，在FPGA中并不容易。我们在软件中通过时延约束来控制设计实现。	[2003-6-10 11:34:16]
[问：ljp]	Spartan-3的成本降低是否得益于90nm工艺？
[答：Danny]	Yes. The price drop due to 3 main reasons(1) 90nm compare with 130nm, it will have 30~40% die size decrease(2) 12 inches wafer vs 8 inches wafer. So each wafer has more die then before(3) remove some un-necessary feature from Virtex-II series which is not demand by consumer proudct. By combine this all three technique, it end up Spartan-3 is 80% price lower than other FPGA vendor can offer	[2003-6-10 11:37:39]
[问：jaa]	spartan-3 提供什么cpu ip core？
[答：Lijinhua]	spartan-3 提供 MicroBlaze,PicoBlaze,8051等其他软CPU核。	[2003-6-10 11:41:30]
[问：samire]	请介绍数字时钟管理功能（DCM），它控制的时钟精度和稳定度有多高？
[答：Hans]	DCM features:programmable skewZero-delay bufferdeskew system clockssystem clock mirroringclock cleaning and duty cycle correctionwide range frequency synthesisfine tuning phase shiftingallowable cycle-to-cycle jitter at clkin is +/- 100ps	[2003-6-10 11:44:57]
[问：science]	现在是否有Spartan-3在通信方面的应用的成功案例？
[答：Danny]	Yes. Couple of telecom customer use S-3 on- router (intellegence)- switching networking- MAN/WAN networking- xDSL application	[2003-6-10 11:46:07]
[问：song yong966]	请问spartan3相应的设计平台是哪一款？
[答：Hans]	ISE5.2I Foundation + SP3 support up to XC3S2000.	[2003-6-10 11:47:08]
[问：samxie]	xilinx 有象Altera Nios 那样的嵌入处理器方案吗? 如果有,有哪些开发工具和RTOS的支持?
[答：Lijinhua]	有。Xilinx提供MicroBlaze软CPU核，在Virtex-II Pro中还支持多达4个Power PC405硬件CPU核。Xilinx的设计软件包EDK＋ISE5.2已经可以支持对这两种CPU的开发。如果要用PPC405并支持RTOS，你可以用VxWorks或MontaVista的Linux.	[2003-6-10 11:50:35]
[问：jaa]	spartan 3 的 cpu ip 达到多少mips
[答：Lijinhua]	spartan 3 的 cpu ip 达到68mips 使用1050LCs.	[2003-6-10 11:51:56]
[问：xiangx]	BUFG有几个？其他管的输入能否作为时钟应用？
[答：Hans]	有8个BUFG非时钟管脚输入可用FPGA的第二时钟资源来当时钟应用。在UCF文件中指定。	[2003-6-10 11:52:44]
[问：netwoof]	现在ALTERA公司的SOPC开发软件在SOC系统的开发中的给我们开发人员提供了很多的IP核,请问XILINX有没有与此功能相似的开发软件呢?
[答：Hans]	有！XILINX提供EDK开发软件来开发SOC,支持PowerPC和MicroBlaze,提供很多IP核使用。	[2003-6-10 11:56:52]
[问：eewwu]	Is the reference clockof a DLL need to bea 50% duty cycle clock?Can I use the signal edgein data which may be notstrictly periodic as thereference of some DLL?
[答：Lijinhua]	No. The reference clock of a DLL didn"t need 50% duty cycle clock. But they must be matched input plus width spec required.No. Because the DLL required max 300pS Cycle-to-Cycle input Jitter.	[2003-6-10 11:57:51]
[问：greycake]	请问DCM的左右具体是什么？如果不出现输入输出的0相位，会出现什么现象？这一点我还没有遇到过？
[答：Danny]	DCM is Digital clock management. With this build in feature, customer can mulitiplier or divide the input clock into the frequency which he wants to run internally of FPGA. With this DCM, customer also can control the phrase shift. With this clock phrase shift capability, customer can easilier to adjust the input and output clock phrase in order to make it synchronize or have a constant phrase shift between in and out clock.	[2003-6-10 12:00:28]
[问：qin]	请介绍系统门，逻辑门和逻辑单元之间的量的关系。
[答：Hans]	它们之间没有直接的量的关系。对FPGA来说，逻辑单元比较有意义。system gate include 20-30% of CLBs used as RAMlogic cell is defined as a 4 input LUT and Flip-flop and carry logic.	[2003-6-10 12:01:24]
[问：Laws on_jian]	SPARTAN-3的DCM可以实现任意相位延时吗？
[答：Danny]	S-3 DCM can do clock multiplication and division based on following equation. Clock input * m/n (where m = 2 to 32, n = 1 to 32)S-3 DCM support Granular phase shift feature (Clkin/256)	[2003-6-10 12:02:29]
[问：ljp]	除了工艺不同，Spartan-3和Virtex-II的功能有何改变？设计软件兼容吗？
[答：Lijinhua]	Spartan-3和Virtex-II在功能方面没有太大的变化，只是CLB有一半的Slice不支持分布式RAM，且取消了BUFT支持。这样，你的HDL设计基本上不需改变，只需要重新综合一次就行了（除了要对内部三态作相应处理）。	[2003-6-10 12:03:25]
[问：chnmy]	请问一下支持Spartan3的ISE是哪个版本？另外它的DCM输入的时钟最大频率是多少？
[答：Danny]	Spartan-3 input clock frequency from 25Mhz to 325Mhz.? All ISE 5.2i (WebPack, Foundation, BaseX and Alliance) supports the whole series of S-3	[2003-6-10 12:03:56]
[问：samire]	请介绍数控阻抗（DCI）的含义。
[答：Hans]	DCI用于传输线的阻抗匹配，防止信号的反射以提高信号的完整性。有了DCM就无需板上放太多的电阻。	[2003-6-10 12:05:57]
[问：ljp]	Spartan-3的时钟管理是动态的吗？它对功耗的降低有何作用？
[答：Danny]	DCM provides phase locking,phase shifting, and synthesizing precise frequencies. Muliple outputs from a single DCM can be used for efficient clock control while using a single resource. For deep submicron process technologies, the digital implementation of these system provides a higher level of stability compared with analog implementations and also eliminates the need for specialized analog power supplies. This enhanced clocking not only provies greater flexibility but also eliminates external clock management chips. This lowers overall system cost and provides higher reliability	[2003-6-10 12:07:50]

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