| 主题:FPGA
DSP 解決方案 |
| 在线问答: |
| [问：shoes_faho] |
針對3種乘法器,如何用語法實現?? |
| [答：Allan] |
you can use lpm_mult and tell quartus to use dedicated multiplier or
LE to implement it.As to softmultiplier, you need to calculate the
results of multiplier and store it into the internal memory(ROM) |
[2003-12-24 10:35:10] |
| [问：jason_lin] |
Where I can find Stratix tools source and
user guide better chinese version. Where I can get more train information
in Taiwan or on this site? |
| [答：Matte] |
You can get the source and user guide from ALTERA Web or connect with
GALAXY in TAIWAN.tel:02-89132200. |
[2003-12-24 10:36:08] |
| [问：elvenyh] |
现有一个有关视频的项目，图象为800*600左右，12BIT的量化，要做一些修正，精确到每一个像素，要求实时处理，每秒50帧，请推荐一款较适合的芯片！现在打算用FPGA+DSP来实现。 |
| [答：Allan] |
you can use altera stratix 1s25 or other stratix device, and use NIOS
to implement the internal processor, and then implement other dsp function
in the fpga |
[2003-12-24 10:37:16] |
| [问：lilixue] |
dsp的速度和芯片资源占用估计？ |
| [答：Mark] |
我们的DSP是用户可配置的，其速度与占用资源与用户的配置有密切的关系。 |
[2003-12-24 10:39:55] |
| [问：tonysw.tw] |
請問我能用FLEX10K系列作你說的功能嗎 |
| [答：Mark] |
请列出您想做的功能 |
[2003-12-24 10:41:52] |
| [问：gycsu] |
Do you have the evaluation version of the
complier for us to try? |
| [答：Mark] |
Yes ,we have. |
[2003-12-24 10:45:32] |
| [问：hanxin] |
一般的dsp系统都是使用dsp＋fpga/cpld的方式来进行设计，使用altera的Fpga
dsp是不是就可以省掉dsp，进行单独设计？ |
| [答：Allan] |
you can use the NIOS from altera to replace dsp(from other
company) |
[2003-12-24 10:45:49] |
| [问：lflyingstar] |
请问3种乘法器的使用中各在何种情况下优选？ |
| [答：Mark] |
根据您的系统资源情况及要求得速度进行选择。速度不重要时可选软乘法，速度要求很高时可使用硬乘法， |
[2003-12-24 10:49:02] |
| [问：lileiming888] |
请问用FPGA设计的硬件加速模块在与主处理器合作时的硬件加速方式有哪几种?谢谢 |
| [答：Allan] |
what the hardware accerator we refer to, is that we use this dedicated
hardware to implement some function, such as filter, viterbi, while the
main processor will use this resource to do the required operation. for
example, the filter operation, previously if implemented by the main
processor, it will take many clock cycles, currently when to use filter
hardware accerator, perhaps it will only take one or a few clock
cycle. |
[2003-12-24 10:52:02] |
| [问：Denstrong] |
Which software is good at FPGA design in the
current. |
| [答：Elliott] |
dear sir Altera Quartus is better than others , it has intimate
GUI, more convenient operate, easy learnform FPGA, and DSPBuilder this
software, you can faster create your design. |
[2003-12-24 10:52:15] |
| [问：chen
mingke217] |
现在要做一个自适应滤波器做线性预测，是否有LMS算法或RLS算法的ip
core，最快速度能达到多少？ |
| [答：Allan] |
currently altera does not have such IP core, could you please check
some other 3rd IP vendors. |
[2003-12-24 10:52:55] |
| [问：shoes_faho] |
你所說的fpga均為低電壓的晶片,有5v較新的晶片系統??以及新的軟件有支援5v系統嗎? |
| [答：Mark] |
FPGA 的 CORE电压和IO电压是独立分开的，对于FPGA的IO支持1.5V 1.8V 2.5V.3.3V 5V
等多种电压标准 |
[2003-12-24 10:53:05] |
| [问：fzld] |
需要对CDMA(IS_95)做PN CODE 捕获,跟踪,有相关的IP
CORE吗?选哪一种芯片? |
| [答：Allan] |
no, altera does not have such a IP core. But I think this typical
algorithm can be implemented by yourself using altera stratix
chip.It is not that difficult to implement the functionality of PN
code searching and tracking. |
[2003-12-24 10:55:32] |
| [问：lileiming888] |
请问用fpga设计一个协处理器，它与主处理器是如何合作工作的？主处理器是把协处理器当作是硬函数对待的,但是如何执行呢?是通过创建新的汇编语言吗? |
| [答：Andy] |
Yes, you can connect your circuit in FPGA via "interface to user
logic" of NIOS. |
[2003-12-24 10:56:28] |
| [问：pengkung] |
Can use dsp in cyclone device? |
| [答：Elliott] |
no, it can"t.cyclone don"t have DSP hardware architecture,so you
only use APEX, startix and startix GX. |
[2003-12-24 10:58:25] |
| [问：mcu8] |
如何获得开发工具？如何获得培训得机会？谢谢！ |
| [答：Matte] |
You can download the Quartus II. MAX+PLUS II... software and more and
more information from the ALTERA WEB. |
[2003-12-24 10:58:40] |
| [问：mcu8] |
如何配置FPGA上DSP资源，如何选型！IP核如何得到？ |
| [答：Allan] |
If you want to use altera stratix device to do some dsp applications,
I think you can use dspbuider to implement your algorithms and then
dspbuilder can generate HDL source code.By the way, altera provide
a lot of dsp ip cores, you can also use these ip core in the enviroment of
dspbuilder.As to how to get these IP core, you can firstly
evaluate these altera IP core without any pay, after evaluation, you can
decide whether to buy it or not. please refer to
http://www.altera.com/products/ip/dsp/ipm-index.jsp |
[2003-12-24 10:59:07] |
| [问：ljp] |
Which type of encryption technology do you
prefer in FPGA DSP design? |
| [答：Allan] |
that depends on your applicaiton! |
[2003-12-24 10:59:46] |
| [问：emperor1015] |
若產品大量生產，FPGA DSP適用嗎? |
| [答：Elliott] |
可以，當你研發完成後，可以透過Quartus做成Hardcopy, 進而大量生產。 |
[2003-12-24 11:01:50] |
| [问：蔣宏浩] |
希望能提供EMULATION BOARD , 比以前的FLEX10K的SOLUTION
.內含SDRAM 和 FLASH 機制 |
| [答：Andy] |
Dear Sir,There are several emulation boards may match your
requirement,1.NIOS CYCLONE2.NIOS STRATIX3.NIOS STRATIX
PROFESSIONAL |
[2003-12-24 11:02:13] |
| [问：lflyingstar] |
请问应用它们的软件都有什么？支持什么语言？ |
| [答：Allan] |
If you mean the software from altera, I think, from our website
http://www.altera.com/products/software/sfw-index.jsp, You can
find all the sw altera provided.As to languages, if you mean the
languages used in fpga design, I think verilog or VHDL are all supported,
if you mean the languages used in nios embedded system, C is the language
used. |
[2003-12-24 11:02:55] |
| [问：jeenwu] |
甚麼是FPGA??甚麼又是C代碼的可編程邏輯設計?? |
| [答：Andy] |
1.Field Programmable Gate Array.2.NO, you should use Verilog,
VHDL, AHDL or Schematic circuit to design it. |
[2003-12-24 11:06:26] |
| [问：qin] |
Could you please tell me the difference
between FFT and IFFT? What is useful for IFFT? |
| [答：Mark] |
This is a theoretically problem .Please reference the teaching
material on DSP . |
[2003-12-24 11:07:21] |
| [问：qzhu] |
IS ip core free? All or
somthing? |
| [答：Matte] |
No,IP core need the charge,but ALTERA support Opencore Evaluation.
Adds Ability for Customers to Test Core in HW for a
Limited Time.1.Requires a license2.Requires a separate
time-limited coreThe Opencore all shown on the IP
Megastore. |
[2003-12-24 11:09:16] |
| [问：bibiwy] |
目前的QUARTUS软件需要的系统配置如何？另外它对AHDL还继续支持吗？ |
| [答：Mark] |
pII400以上 winnt 4.0 或win98以上对ahdl继续支持 |
[2003-12-24 11:10:09] |
| [问：shoes_faho] |
請問有 5v 容量較大的晶片以及新的發展系統 |
| [答：Elliott] |
目前Altera只有Max7000s的CPLD,
對FPGA來說容量越大，且製程越先進，電壓只是會越小。而ALTERA目前FPGA的發展系統有QuartusII 3.0
sp2,不久QuartusII 4.0也將出現，您有興趣可以再進一步跟我們聯絡。 |
[2003-12-24 11:10:19] |
| [问：liang-chiao] |
請問"interface to user logic"與"Custom
Instructions"的方式有何不同? |
| [答：Allan] |
1. the co-processor will be a peripheral of NIOS2. the
co-processor will be an function unit to execute user
instruction. |
[2003-12-24 11:12:48] |
| [问：samire] |
目前FPGA實現的DSP和通常的DSP相比,性能和使用上有何優點? |
| [答：Allan] |
as I say during the presentation, fpga dsp will be a complement to the
traditional dsp.Usually FPGA DSP will be used to implement those
functions which are speed critical. Such as viterbi, FIR, RS,
etc. |
[2003-12-24 11:15:00] |
| [问：wfeng26] |
How much for the DSP Developemnt
Kit? |
| [答：Andy] |
List Price on WEB SITE is DSP Development Kit, Stratix
EditionStratix EP1S25 $1,995DSP Development Kit, Stratix
Professional EditionStratix FPGA Stratix EP1S80 $4,995If you
want more information about it, please contact GALAXY PM, HUGH,
hughk860@gfec.com.tw, thanks. |
[2003-12-24 11:17:15] |
| [问：amaosonic] |
对于configruable DSPs 会不会因为灵活性太大，而需要用户对含有dsp
block的FPGA结构及功能了解过于深入？ |
| [答：Mark] |
不需要，只要对dsp FPGA的结构和功能有一定的了解就可以了，很多细节的工作会有软件帮您完成的 |
[2003-12-24 11:19:03] |
| [问：CWIN] |
Does the performance of DSP Builder is
good? Does it cost more LE than hand-writing codes? |
| [答：Allan] |
what do you mean the performance of dsp builder?DSP builder is
a platform that many engineers can work on to develop DSP,not only FPGA
engineer, but also algorithm develop engineer.It will be very
convenient for engineers to implement dsp applications. |
[2003-12-24 11:19:06] |
| [问：xufeng5581] |
请问这种芯片适合于数码相机吗，若做3M+MP3播放的数码相机，可否推荐一款芯片，谢谢 |
| [答：Matte] |
You can think about the Stratix.Because The Stratix provides
memory block structures, and DSP blocks. |
[2003-12-24 11:19:40] |
| [问：CWIN] |
How many LEs does the NIOS embeeded
processor cost? |
| [答：Allan] |
the mininum NIOS system only costs less than 1000LE |
[2003-12-24 11:19:50] |
| [问：darshou] |
面对越来越便宜但是功能强大的专用多媒体处理芯片，如果再想用fpga增加其他功能，所增加的价格是设计的瓶颈请问在技术提高和功能保持的基础上，fpga的价格会有多大空间？ |
| [答：Andy] |
Dear Sir,About your question, please contact GALAXY PM, HUGH,
hughk860@gfec.com.twThanks |
[2003-12-24 11:21:05] |
| [问：chen
mingke217] |
如果要做矩阵相乘，用何芯片合适？ |
| [答：Mark] |
需要看您的系统需求（资源和速度）来综合考虑 |
[2003-12-24 11:22:08] |
| [问：qzhu] |
The bands widths is enough,while I want to
know how much the stratix"s speed is? |
| [答：Elliott] |
the stratix high speed I/O can to 840Mbps, PLL output can to 422MHz,
but the clock speed depend on your design. |
[2003-12-24 11:23:08] |
| [问：liang-chiao] |
請問CYCLONE是否可做NIOS+DSP的功能? |
| [答：Andy] |
Yes, sure, but you can get more high performance on DSP if you choose
STRATIX. |
[2003-12-24 11:26:00] |
| [问：tonysw.tw] |
我想用FLEX10K作fir濾波器 |
| [答：Elliott] |
你可以用HDL作濾波器在FLEX10K但作出來的效能並不會很好，建議您用Startix會比較好 |
[2003-12-24 11:26:33] |
| [问：amaosonic] |
软乘法实现的时候，不占用逻辑资源，那么需要编译或是硬件的支持吗？
它存放结果的表格，是事先做好的？ 还是动态更新？ |
| [答：Allan] |
soft multiplier will use the internal memory to store the multiplier
results, altmemmult megafunction can be used to do RAM-based signed or
unsigned multiplier functions. |
[2003-12-24 11:27:20] |
| [问：amaosonic] |
dsp builder 可以单独用来做设计吗？还是必须和matlab或是sopc
builder合用呢？ |
| [答：Allan] |
dspbuilder is integrated with matlab/simulink. |
[2003-12-24 11:28:09] |
| [问：samire] |
FPGA中的DSP設計可重新編程多少次? |
| [答：Andy] |
Limitless. |
[2003-12-24 11:28:15] |
| [问：qzhu] |
Will the HDL code generated by
DSP builder use more resource? |
| [答：Mark] |
No,It wouldn"t use more resource. |
[2003-12-24 11:29:46] |
| [问：liang-chiao] |
"interface to user logic"與"Custom
Instruction"之執行效能有何差別? |
| [答：Allan] |
1. as nios peripheral2. as instruction execution unit |
[2003-12-24 11:30:10] |
| [问：lileiming888] |
用FPGA实现的DSP处理模块如何和通用的DSP处理器(如TI,AD公司的处理器)结合使用,比如把FPGA当作协处理器来用,那通用DSP处理器如何调用FPGA呢?使用通用DSP的现有汇编语言可以实现调用吗?谢谢. |
| [答：Allan] |
there is an example of my presentation. |
[2003-12-24 11:31:23] |
| [问：zxhweb] |
ALTERA的FPGA在保密性方面有那些措施？ |
| [答：Mark] |
您可在设计调试完成后转成hardcopy 芯片 |
[2003-12-24 11:31:35] |
| [问：lihongwx] |
如何实现三角函数？ |
| [答：Allan] |
you can use write nios sw to implement it |
[2003-12-24 11:32:51] |
| [问：mysky163] |
FPGA在ＰＣＢ布板时的注意事项？ |
| [答：Matte] |
1.Reduces system noise by filtering and evenly distributing power
toall devices2. Terminates the signal line to diminish signal
reflection3. Minimizes crosstalk between parallel traces4. Reduces
the effects of ground bounce5. Matches impedance |
[2003-12-24 11:33:51] |
| [问：zxhweb] |
你好，请问CYCLONE系列的PLL的AGND是真正的模拟地吗？它对我的系统的模拟的会造成干扰吗？ |
| [答：Mark] |
PLL不会对您的系统的模拟信号造成干扰，因为它是集成在芯片内部，和您的模拟信号处理隔离的 |
[2003-12-24 11:34:22] |
| [问：hanxin] |
能不能简单的介绍一下fpga
dsp的应用领域，主要是已经有较成熟的应用方面，谢谢！ |
| [答：Allan] |
communication, video/audio, etc. ref to my presentation |
[2003-12-24 11:34:27] |
| [问：hanxin] |
fpga
dsp的抗干扰性能如何，在其内部做了哪些抗干扰措施？ |
| [答：Mark] |
FPGA DSP的抗干扰性能就是FPGA的抗干扰性能，请参阅我们的数据手册 |
[2003-12-24 11:36:25] |
| [问：charmaine] |
Compared with the dsp of TI,what"s the
advantages of your products? |
| [答：Elliott] |
Use Quartus add DSPBuilder, you can short develop time and
customizable cpu, memory, bus, and user-defined hardware accelerator
block.and it"s cost. |
[2003-12-24 11:36:50] |
| [问：lihongwx] |
功耗和浪涌电流多大？供电设计需要注意什么？ |
| [答：Andy] |
Dear Sir,1.It depend on what device you use, and how many resourse
in FPGA you used and what speed is your design.2. Basically, there are
several power need to support to a FPGA, at the first is VCCINT,
Digital Power,second is VCCIO,Digital Power,if there is PLLs on
your device, you should offer a analog VCCIO to it.The detail
information, please check the datasheet of the device. |
[2003-12-24 11:40:05] |
| [问：hanxin] |
ALTERA的fpga
dsp在电力系统保护及继电保护系统方面有没有比较经典的应用案例 |
| [答：Allan] |
you can use fpga dsp solution, but currently we do not have such
application examples |
[2003-12-24 11:40:18] |
| [问：lotusyan] |
How much is for development kit of
FPGA? |
| [答：Mark] |
This question you need ask you local sales . |
[2003-12-24 11:41:10] |
| [问：vanderchen] |
若用FPGA實現DSP控制器,則A/D和D/A的部份是否外加? |
| [答：Matte] |
Yes.FPGA實現DSP控制器需外加A/D和D/A. |
[2003-12-24 11:43:53] |
| [问：ljp] |
Tell me more detail the performance of Hard,
Logic and Soft multiplier? Which one is more suitable for DSP design in
FPGA? |
| [答：Allan] |
hard multiplier and soft multiplier is useful for high performance
multipler(high speed), logic multiplier is very useful for small
multipliers such as 6x6.Page 16 of my presentation |
[2003-12-24 11:44:45] |
| [问：theprimegod] |
请举几个这两者关联使用的例子，因为我对此缺乏概念。 |
| [答：Allan] |
which example? this question is not clear |
[2003-12-24 11:45:28] |
| [问：zxhweb] |
另外FPGA的RAM如何使用？ |
| [答：Elliott] |
你可以使用 Quartus的megawize建立RAM，這會比較方便你使用，且也較能增加performemce. |
[2003-12-24 11:45:57] |
| [问：lihongwx] |
如果我要实现640*480的实时图像处理（插补，灰度变换，扇形变换等），需要用何种型号？ |
| [答：Allan] |
you can use stratix 1s25 FPGA |
[2003-12-24 11:48:19] |
| [问：kychen] |
目前你們的產品在市場上實際應用在哪些層面..實際商品 |
| [答：Andy] |
Dear Sir,About your question, please contact GLAXY PM,
HUGH,hughk860@gfec.com.tw |
[2003-12-24 11:49:43] |
| [问：lihongwx] |
芯片的保密性如何？ |
| [答：Mark] |
如果您将您的设计转为hardcopy， 没有任何常规方法可以解密 |
[2003-12-24 11:49:45] |
| [问：lien.shin] |
您好 請問A.FPGA
DSP是針對何種條件下的環境使用,最適當.最有效率,B.它又比傳統設計環境,快多少百分比C.要使用它需要具備何種條件,才能上手D.要使用它需要付出多少錢NT$請回答 謝謝 SUNNY 2003-12-24 |
| [答：Elliott] |
a:使用stratix系列的晶片開發b:比TI晶片快c:有學習過mathab和HDL的背景d:請聯絡茂綸，將與您詳談。 |
[2003-12-24 11:52:49] |
| [主持人：ChinaECNet] |
恭喜您，giant101！經過電腦抽獎您在本次座談中獲得一部MP3播放器。請網名為giant101的用戶與中電網聯繫(8862-25222282
Virginia 或 smedia@ms5.hinet.net)。 |
[2003-12-24 11:53:24] |
| [主持人：ChinaECNet] |
歡迎各位填寫線上座談頁面的問卷調查，並請于明天中午12點以前提交。 |
[2003-12-24 11:53:45] |
| [主持人：ChinaECNet] |
中電網開辦的“工程師之家/線上座談”欄目，是中電網向中國電子元器件領域廣大廠商、科研人員和工程師們推薦、推廣新產品、新技術、新應用而推出的一項重要的技術教育、培訓和支持活動。在這項活動中，中電網會不斷邀請一些世界著名電子元器件供應商的高級技術或高級經營管理人員主講國際半導體科技最新進展、電子元器件最新產品及其應用、全球半導體市場等方面的內容，著力構建起國內外同行業間直接技術交流的橋樑。希望在各位聽眾（網友）的積極參與下，中電網“線上座談”能越辦越好，其影響範圍越來越廣！ |
[2003-12-24 11:54:04] |
| [主持人：ChinaECNet] |
祝大家事業有成、生活愉快！歡迎多提寶貴意見，歡迎關注中電網，下次再見。 |
[2003-12-24 11:54:16] |
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