鍦ㄧ嚎搴ц皥

鐑棬鍏抽敭瀛�: 瑙ｅ瘑 鍥介檯鏍囧噯 灏佽鎶€鏈� NOR 

鍏充簬鏈搴ц皥

搴ц皥绠€浠�

MAX II CPLD鍣ㄤ欢鍏锋湁鎴愭湰浼樺寲鐨勪綋绯�,浣庡姛鑰�,鐢ㄦ埛Flash瀛樺偍鍣�,瀹炴椂鍦ㄧ郴缁熷彲缂栫▼鎬э紙ISP锛�,MultiVolt? 鏍哥伒娲绘€�,JTAG瑙ｉ噴鍣ㄥ拰瀹规槗浣跨敤鐨勮蒋浠剁瓑鎬ц兘,鑳藉彇浠ｆ洿鏄傝吹鎴栧姛鑰楁洿楂樼殑FPGA銆丄SSP鍜屾爣鍑嗛€昏緫鍣ㄤ欢,鑳藉疄鐜伴珮搴︾殑鍔熻兘闆嗘垚锛屽噺灏忕郴缁熻璁℃垚鏈€傚湪鍚勭鎺у埗搴旂敤涓涓婄數椤哄簭,绯荤粺閰嶇疆,I/O鎵╁睍鍜屾帴鍙ｆˉ鎺ョ瓑鏈夌潃骞挎硾鐨勭敤澶�.

绮惧僵闂瓟

涓婚:浣跨敤MAX II CPLD闄嶄綆绯荤当鎴愭湰绡€鐪侀枊鐧兼檪闁�
鍦ㄧ嚎闂瓟:
[闂細Anoymous] What are the reference prices? 
[绛旓細Susan] Galaxy will give you more detail pricing information after this seminar.  Thanks.  [2004-4-6 10:29:51]
[闂細Anoymous] 鎮ㄥソ,鎴戞瘡娆″湪瑷▓鐨勬檪鍊�,濡傛灉鎶奀PLD鐨刴arco cells瀹归噺鐢ㄧ洝,鍦≧un鏅傜櫦鐝炬韩搴︾附鏄亷鐔�,澶х磩鍦�60~70搴﹀乏鍙�,闈炲父鐕欐墜,鏄惁鍦ㄧ祫璀垨瑷▓绋嬪紡鏅傛湁瑷畾闇€娉ㄦ剰鐨�?鎴栬€呴€欐ǎ鐨勯珮婧爆鏂兼甯稿憿? 
[绛旓細Andy] Hi,璜嬪晱鑸囦綘CPLD鐩告帴鐨処C鏄惁娑堣€楅潪甯稿鐨勯浕鍔�?  [2004-4-6 10:31:06]
[闂細tanzhirong1] MAX II鐨勫競鍦哄畾浣嶅湪鍝釜灞傛锛熶及璁＄敤鎴蜂娇鐢ㄥ畠鍋氳璁＄殑鎴愭湰鏄灏� 
[绛旓細Andy] 瀹冧富瑕佹槸鍋氱偤涓嶅悓device闁撶殑鐨勪粙闈�,鎴朓/O expansion,address decoding鎴栨槸涓嶅悓闆诲婧栦綅闁撶殑淇¤櫉鐣堕渶瑕佸仛杞夋彌鏅傚彟澶�,鍙敤maxii鑸囦竴鍊媐lash渚嗗彇浠ｅ偝绲辩殑configuration device.  [2004-4-6 10:37:09]
[闂細chengates] 浣跨敤AHDL鏂糓AX+plusII10.2COMPILER閬庣殑妾旀,鍙惁鐩存帴鐩稿鏂糓AX II CPLDs 
[绛旓細Andy] Dear Sir,MAXII device only support QuartusII.you have to recompile in QuartusII.  [2004-4-6 10:38:05]
[闂細ritashih] 鑻ュ師鏈偤acex1k鐨刣esign,鍙惁瀹屽叏绉绘鑷矼AXII鏋舵瑁�? 鏈夊惁闇€淇鐨勯儴鍒�? 
[绛旓細Elliott] This is must by design,but all most can mageration to MAXII.  [2004-4-6 10:41:25]
[闂細pantinjin] 鎴戜笉鐭ラ亾鎬庢牱鎶婂簳灞傚仛涓诲眰鏉ヨ蛋绾匡紝骞舵敼鍙樿蛋绾跨殑澶у皬銆� 
[绛旓細Andy] Dear Sir,about the routing,quartusII40 can provide best result automatically.if you need to improve the result,you can adjust settings in QuartusII.you can leave your tel number to kevinc801@gfec.com.tw  [2004-4-6 10:41:57]
[闂細qzhu] I hope to hnow the max speed of MAX II CPLD and resouce. 
[绛旓細Andy] Dear Sir,because the MAXII is a all new architecture with newest .18um process.so,it can provide 200Mhz performance and very efficient resource usage.anyway,the Fmax is depend on your design size,architecture, even coding style.  [2004-4-6 10:44:32]
[闂細dboyman] MAX II CPLD鍦ㄥ紑鍙戝ぇ瑙勬ā闆嗘垚鐢佃矾绯荤粺鏃讹紝涓嶸HDL绛夋弿杩拌瑷€缁撳悎ASIC姣旇緝濂借薄浼樺娍涓嶆槸澶槑鏄撅紝鎬庢牱鍙栬垗瀹冧滑锛� 
[绛旓細Andy] Dear Sir,actually,QuartusII40 can support VHDL,AHDL,Verilog and schematic. but, ASIC design flow only supports pure VHDL and Verilog.if you will transfer design to ASIC flow,i suggest you to write "pure" VHDL or Verilog.in addition, MAXII can provide lowest cost. i don"t suggest you to transfer CPLD design to ASIC.  [2004-4-6 10:49:20]
[闂細luker112] 鐜板湪宸叉湁QUARTUS锛岄偅楹界敤MAX II 杩樻湁浠€楹戒紭鍔垮憿 
[绛旓細Elliott] MAXII"s feature Low power, High density, User flash menory,ISP,MultiVolt coreMultiTrack Interface,MultiTrack Interconnect.  [2004-4-6 10:50:51]
[闂細Renlisheng] 1. MAX II CPLD寮€鍙戝伐鍏蜂环鏍硷紵2. MAX II CPLD鑺墖浠锋牸锛�3. MAX II CPLD鍚岀骇鑺墖浼樼己鐐规瘮杈冿紵 
[绛旓細Hugh] MAx II CPLD"s FeatureLow PowerHigh DensityUser Flash MemoryReal-Time-In-System Programmability(ISP)MultiVolt CoreMultiVlot I/O InterfaceMultirack interconnect, JTAG Translator.  [2004-4-6 10:52:09]
[闂細mi040606] What is the difference between PLD and CPLD? 
[绛旓細Susan] PLD is general term for all programmable logic device.  CPLD is complex programmable logic device.  It has instant on, non-volatile and reprogrammable, single chip features.  [2004-4-6 10:52:33]
[闂細boblin0319] MAX-II 鏀寔LVDS鍡�? 鎿嶄綔閫熷害鍙互鏈夊蹇�? 
[绛旓細Andy] Dear Sir,maxII only suppot TTL,CMOS,PCIthe operating speed is depend on design.  [2004-4-6 10:53:09]
[闂細寮犳尟鍧 濡備綍娑堥櫎缁勫悎閫昏緫浜х敓鐨勬瘺鍒�? 
[绛旓細Andy] Dear Sir,you can refer to some digital design textbook.for example: if a FSM"s state translate has glitch,you can adjust the state encoding.  [2004-4-6 10:55:16]
[闂細qin] 鍦ㄨ姱鐗囧皝瑁呰〃涓紝鏍囨敞闀垮害涓�9.00BSC, BSC琛ㄧず浠€涔堟剰鎬�? 
[绛旓細Elliott] BSC is Basic Spacing between Centers  [2004-4-6 10:55:26]
[闂細eikijoe] 鎴戠殑闆昏矾瑷▓涓婅垏CPLD鐩告帴鐨勫湴鏂逛甫鐒℃秷鑰楄ū澶氶浕鍔�,鍚屾ǎ鐨勮ō瑷�,鎴戝彧瑕佷笉鎶妋arco cells鐨勫閲忓婊�,灏变笉鏈冨緢鐕�,浣嗘槸涓€瀵豢浠ュ緦,灏卞咕涔庡彲浠ョ叜铔嬩簡 
[绛旓細Andy] Dear Sir,did you try the design in different device?and, i think your problem can be solved by adjustsynthesis or fit setting.  [2004-4-6 10:56:40]
[闂細happyfish] 鏂扮敘鍝佹瘮涓€浠ｇ敘鍝佹湁浠€楹间笉涓€妯ｏ紝澶氫簡浠€鏂板姛鑳� 
[绛旓細Matte] Low Power,High Density,User Flash Memory, ISP,MultiVolt Core,Multivolt I/O interface,MultiTrack Interconnect,JATG Translator.  [2004-4-6 10:57:15]
[闂細qin] CPLD鍣ㄤ欢鍦ㄥ鏃堕挓绯荤粺璁捐涓湁浣曠壒鍒殑娉ㄦ剰浜嬮」? 
[绛旓細Elliott] 1.Don.t use geted clk2.Need to use global clk  [2004-4-6 10:58:15]
[闂細xyuding] 鐩稿浜庡緢澶氱殑IO鑰岃█锛孡E灏戜簡浜涖€俶ax2鎴栬鍙兘鐢ㄤ簬鐗规畩鍦哄悎銆� 
[绛旓細Susan] MAX II is CPLD product, which targets low to mid density range designs.  Also for most of CPLD applications are bus bridging, I/O expansion etc.  They requires more I/O than LE.  If you need more LE for your design, please refer our FPGA (Cyclone or Straix) families.  [2004-4-6 10:58:56]
[闂細liu-0315] How about the speed of the MAX II? 
[绛旓細Andy] Dear Sir,the operating speed is depended on design,architecture, coding style...  [2004-4-6 10:59:01]
[闂細wjl27] 鎴戜娇鐢ㄧ殑鏄疢AXPLUS 2杞欢,鑰岄潪QUARTS ,閭ｄ箞鑳藉惁鍦∕AXPLUS涓婁娇鐢�?鐜板湪鑳藉惁鎻愪緵鏍风墖? 
[绛旓細Matte] Not,The MaxPlusII not support the MAXII.  [2004-4-6 10:59:46]
[闂細RockHuang] 璜嬪晱璨村叕鍙哥殑瀹㈡埗浠PLD閲忕敘鏅傦紝瀵﹂殯鑹巼澶ф澶氬皯锛� 
[绛旓細Andy] Dear Sir,Sorry Sir,yield rate is the confidential data of a Fab.  [2004-4-6 10:59:53]
[闂細jack] 璜嬪晱 MAX II 鏄惁鍙湅鎴愬皬鍨嬬殑 FPGA + Download Flash ? 鎴栬€呭拰涓€鑸� FPGA 鏈€澶у樊鐣扮偤浣�? 
[绛旓細Elliott] Yes,瀹冨彲浠ョ暥鎴愪竴鑸皬鍨嬬殑FPGA  [2004-4-6 11:02:19]
[闂細brianaltera] Does MAXII use byteblaster or byteblaster II as programming adapter? 
[绛旓細Matte] Yes,MAXII is using byteblaster or byteblasterII to download.  [2004-4-6 11:02:49]
[闂細onlooker1] 璇烽槓杩癈PLD鍦ㄧ粍鍚堥€昏緫涓庢椂搴忛€昏緫璁捐鏂归潰鐨勪紭鍔� 
[绛旓細Andy] Dear Sir,in MaxII, it uses cyclone-liked architecture.the basic logic element can provide a 4 input LUT and a register.and dedicated carry out generation, LUT,Reg chainsare provided to improve the compilation result.  [2004-4-6 11:02:51]
[涓绘寔浜猴細ChinaECNet] 鍚勪綅瑙€鐪撅紝鐝惧湪鐢ㄦ埗鎻愬晱寰堣复韬嶏紝灏堝姝ｅ湪閫愪竴鍥炵瓟銆傝珛鑰愬績绛夊緟鎮ㄥ晱椤岀殑绛旀锛屽悓涓€鍟忛璜嬩笉瑕佸娆℃彁浜ゃ€�  [2004-4-6 11:03:46]
[闂細mi040606] What is the main advantage of the CPLD and FPGA?Which one is better in cost and performance? 
[绛旓細Susan] It depends on what is your design.  For FPGA, it has rich register resource and has more LE, normally it targets larger, complex and requires a lots of registers designs.  If your design needs more logic, like decoder, than CPLD will be better.  CPLD has advantage at instant on, single chip, and non-Volatility.  FPFA has advantages at high desnities, embedded SRAM, PLLS and IP.  [2004-4-6 11:05:28]
[闂細mi040606] How to use the built-in flip-flop in CPLD for storage data? 
[绛旓細Andy] Dear Sir,you can write/draw the register in your design.if you needs memory, QuartusII will use logic element to implement your memory.in addition,the MAXII can provide user flash,you can use it to store some data.  [2004-4-6 11:05:53]
[闂細Anoymous] 璜嬪晱鍙冭€冨児鏍� 
[绛旓細Susan] We will contact you and provide you more detail pricing information.  [2004-4-6 11:05:53]
[闂細璋㈡枃蹇梋 璇蜂粙缁峯ne-hot鐘舵€佹満涓嶣inary/Gray鐘舵€佹満鐨勭壒鐐�? 
[绛旓細Andy] Dear Sir,binary can save most register.onehot can provide best speed but uses most register.gray can provide a trade off between onehot and binary.  [2004-4-6 11:07:29]
[闂細liu-0315] How many of LE in MAXII?What is the price for  each LE? 
[绛旓細Susan] The LE range for MAX II is from 240 LE to 2210 LE.  We will contac you to provide more detail pricing information.  [2004-4-6 11:07:50]
[闂細liu-0315] What is application area for the CPLD and MAX II? 
[绛旓細Matte] Consumer Products,Communication Products,Computing Products,Battery-PoweredProducts and all logic control .  [2004-4-6 11:07:54]
[闂細qzhu] Can the LVDS signals is used on it with speed 622MHZ? 
[绛旓細Andy] Dear Sir,maxii can"t use LVDS.you can use stratix or stratixGX.  [2004-4-6 11:08:11]
[闂細kwqiang_2000] maxplus 10.2 baseline锛屼豢鐪熺殑鏅傚€欑鍒颁簡涓€浜涢夯鐓╋紝灏辨槸浠跨湡鏅傞枔鍙湁1us锛屼絾鏅傞悩姝ラ暦绔熺劧鏄�200ns锛屼篃灏辨槸鍙湁5鍊嬪懆鏈燂紝澶皯浜嗐€傛湁浣曡睛娉曡В姹洪€欏€嬪晱椤�? 
[绛旓細Andy] you can turn on the File ==> End time to give longer value for you draw the input waveformwhen you open the waveform file.  [2004-4-6 11:10:15]
[闂細Nike-040406] How much for the development kits of MAX II? 
[绛旓細Susan] Our Quartus II web edition supports MAX II product and it is FREE.  Please go to www.altera.com to download the software and request the license.  Also you may contact Galaxy for CD of software.  But you still need to get the license from the Altera Web.  [2004-4-6 11:10:29]
[闂細boblin0319] MAX-II 浠€楹兼檪鍊欏彲渚涜波 
[绛旓細Susan] EPM1270 ES will be ready at July.  EPM240 and EPM570 ES will be ready at Oct.  For all M/P devices will be ready the beginning of 2005.  [2004-4-6 11:11:51]
[闂細bithxm] MAX II鐩墠鍦ㄤ腑鍥界殑渚涜揣鎯呭喌濡備綍锛屽鏋滄槸灏忔壒閲忚璐э紝鍛ㄦ湡澶ф澶氶暱 
[绛旓細Susan] Altera just announced MAX II a month ago. The first silcon of MAX II will be ready at July. For M/P devices will be ready the beginning of 2005. We will contact you for more detail ordering information.  [2004-4-6 11:14:17]
[闂細kwqiang_2000] dcfifo涓殑wrusedw[]鍜宺dusedw[]鏄粈楹�?濡備綍浣跨敤? 
[绛旓細Andy] Dear Sir,you can use the "documentation" tab in megawizard window in QuartusII40.it can provide you the sample waveform and I/O port definition.  [2004-4-6 11:14:40]
[闂細kwqiang_2000] 璜嬪晱濡備綍鍦╩axplusII涓娇鐢ㄥ姛鑳藉韩鍜孖P鏍� 
[绛旓細Elliott] I suggest you to use Quartus II.You can use Mega-Wizard Plug-in Manager to editor Altera library and Altera IP  [2004-4-6 11:15:17]
[闂細寮犳尟鍧 Altera鐨勫摢涓郴鍒桟PLD鏀寔涓夋€佽緭鍑�? 
[绛旓細Andy] Dear Sir,all CPLD families are provided.ex: MAX3000,7000,MAXII  [2004-4-6 11:15:33]
[闂細kwqiang_2000] Altera鐨凜PLD鑸嘑PGA鐩告瘮鏈変綍鍎嫝? 
[绛旓細Susan] For CPLD, it has instant on, low cost, ease of use, non-volatililty and single chip features. For FPGA, it has high densities, fast fmax, embedded SRAM, PLLs, and IP features.  [2004-4-6 11:16:55]
[闂細41070924] 璇烽棶鎴戜娇鐢–PLD瀹炵幇8璺�24涓茶鏁版嵁鐨勫苟琛岃浆鎹紝甯歌鏉ヨ闇€瑕佷粈涔堟牱绾у埆鐨勭墖瀛愶紝濡傛灉鎴戣繕鎯冲湪CPLD涓婂疄鐜拌鏁版嵁FIFO缂撳啿鍛紵鎴戠敤CPLD瀹炵幇缂撳啿鍚堥€傚悧锛� 
[绛旓細Andy] Dear Sir,you can consider the needed I/O number and FIFOsize to choose a suitable device.CPLD can not provide the FIFO. maybe,you can consider the cyclone EP1C3.  [2004-4-6 11:17:48]
[闂細qzhu] Is it compatible with 5V? 
[绛旓細Susan] No.  For 5V design, it requirs other circuits to help.  We will provide the application note for how to use MAX II for 5V design.  [2004-4-6 11:18:06]
[闂細kwqiang_2000] 濡備綍鍚慙PM瀵︾従鐨凴AM涓璩囨枡? 
[绛旓細Matte] You can designers to generate a Memory Initialization File (.mif) to initialize the ROM contents.  [2004-4-6 11:18:45]
[闂細hiarfu] MAX II灏嶆柤鍔熺鐨勯檷浣庢柟娉� 
[绛旓細Andy] Dear Sir,MAXII uses new .18um process and a internal power regular.so,the Vccint can be 3.3V , 2.5V even 1.8V.and, the all new architecture and power management circuits provide a low power consumption.  [2004-4-6 11:20:21]
[闂細kwqiang_2000] 鍦╲erilog鐨勬浉涓婃壘鍒颁竴鍊嬮潪鍚屾娓呴浂d瑙哥櫦鍣ㄧ殑渚嬪瓙锛屽湪quartus涓嵒涓嶈兘閬嬭锛岃珛鍚勪綅楂樻墜鎸囬粸杩锋触锛屾€庨航鎵嶈兘瀵︾従闈炲悓姝ユ竻闆�? 
[绛旓細Andy] Dear Sir,could you provide your error message?  [2004-4-6 11:21:00]
[闂細netstraveler] 浠ユ垜灏岮LTERA鐢㈠搧鐨勭矖娣鸿獚鐭�,鎴戣寰桵AX II鍦ㄨ泊鍏徃鐨勭敘鍝佸畾浣嶆噳瑭叉槸灞柤law cost鐨勭敘鍝�,閭ｈ垏鎿佹湁鍚屾ǎ浣庡児鍎嫝鐨凜yclone鐩告瘮,瀹冨€戜箣闁撴湁浣曞樊鐣�? 
[绛旓細Susan] MAX II is low cost CPLD product and Cyclone is low cost FPGA product.  CPLD and FPGA are different products.  FPGA (Cyclone) has higer densities and rich register.  CPLD (MAX II) is logic rich, non-volatile single chip solution.  From cost poin of view, we can say that MAX II has lowest cost per I/O and Cyclone has lowest cost per LE.  [2004-4-6 11:21:47]
[闂細mimouse] 濡備綍 vhdl,verilog 涓疄鐜板弻鍚戝紑鍏�? 
[绛旓細Elliott] Please go to http://altera.com/support/examples/exm-index.html,it have example  [2004-4-6 11:22:37]
[闂細wjl27] MAX 2 鐨勬椂闂寸骇鍒�?浠栫殑鏃跺簭閫昏緫鑳藉姏瀵规瘮FPGA鐨勮兘鍔涘浣�?  
[绛旓細Susan] The speed grade for MAX II are -3, -4 and -5.  [2004-4-6 11:23:37]
[闂細mimouse] 鎴戞槸杩戞潵鎵嶅紑濮嬪cpld璇█鐨勶紝鍦ㄤ娇鐢╩p2搴旂敤杞欢鏃讹紝鎵撳紑*銆倀df鏂囦欢杩涜EDIT锛涙棤璁烘垜鏄敤VHDL锛孷erilog HDL锛孉BEL 璇█锛堥兘鏄簺绀轰緥锛夛紝鎬绘槸娌″姙娉曢€氳繃,涓轰粈涔�? 
[绛旓細Andy] Dear Sir,i would like to suggest you to use VHDL or Veriloglanguage.  [2004-4-6 11:24:03]
[闂細brianaltera] Dear Sir:  Could I use I2C or SMbus to access the flash in MAXII? 
[绛旓細Elliott] It can use SPI , parrallel and user define.  [2004-4-6 11:24:35]
[闂細brianaltera] Could NIOS fit into MAXII?Is there smaller NIOS available soon? 
[绛旓細Susan] No.  Currently we do not plan for  NIOS solution into MAX II.  We will contact you to discuss your needs for NIOS.  [2004-4-6 11:24:59]
[闂細Oswin] 璜嬪晱涓€涓婹uartusII鐨勫湪瑷▓MAXII鏅傛槸鍚﹀彲浠ョ洿鎺ョ敱澶栭儴绲︿簣CLOCK,涓嶇稉鐢眊lobal clk杓稿叆? 
[绛旓細Andy] Dear Sir,i strongly recommend you to use global clk or dedicated input pins as clock input.  [2004-4-6 11:25:07]
[闂細eikijoe] 鍦ㄦ檪搴忕殑閭忚集瑷▓瑁�,鑻ユ垜鏈皣CLK鎺ヨ叧鎺ヨ嚦GLOBAL CLK鑰屾帴鑷充竴鑸殑I/O鑵充綅,鏈冩湁浠€楹兼ǎ鐨勫晱椤岀櫦鐢�? 
[绛旓細Andy] Dear Sir,it may cause clock skew problem.  [2004-4-6 11:26:31]
[闂細qzhu] Could you tell the max speed of clock. 
[绛旓細Andy] Dear Sir,because the speed is decided by QuartusII compilation and your design, please refer to the compilation report.  [2004-4-6 11:27:40]
[闂細ritas869] MAXII鐨処/O鐐轰綍娌掓湁208PIN 鎴� 240PIN 鐨勫寘瑁�, 涓€涓嬪瓙灏辫烦鍒癇GA鐨勫寘瑁濅簡 
[绛旓細Andy] Dear Sir,it is consider most customers" requirements andlowest cost ....  [2004-4-6 11:28:33]
[闂細chenzhongwen] 姝よ姱鐗囩殑浠锋牸鏄灏戯紵100K鏃� 
[绛旓細Susan] We will contact you to provide more detail information about pricing.  [2004-4-6 11:29:28]
[闂細璋㈡枃蹇梋 浠ｆ浛ISA鐨勮瘧鐮佺數璺拰閫氱敤I/0鎺ュ彛鐢佃矾锛�8255锛変竴鍏�100涓狪/0鍙ｅ乏鍙炽€傝楂樻墜甯繖閫変竴鍧桝ltera鑺墖銆� 
[绛旓細Andy] How about EPM570 144 pin device?or you have other logics and pins to fit in it....maybe you can choose bigger MAXII or cyclone devices.  [2004-4-6 11:30:26]
[闂細Nike-040406] Can you tell us the design flow chart of CPLD? Any difference for the FPGA? 
[绛旓細Matte] The CPLD and FPGA design flow all most same.PLD Design Flow :Design entry-->Synthesis-->P&R-->Timing Analysis-->Simulation-->Program & Test.  [2004-4-6 11:31:16]
[闂細cailiangliang1] 閫氬父鎯呭喌涓嬫槸灏咰PLD鍚孌SP鎴栧崟鐗囨満閰嶅悎浣跨敤锛屽熀浜嶤PLD鍔熻兘杈冨己鐨勭壒鎬ц妭鐪佸紑鍙戞椂闂存槸鍙互鐞嗚В鐨勶紝浣嗕粠浣曢檷浣庢垚鏈垜涓嶅ぇ娓呮銆傝阿璋紒 
[绛旓細Susan] CPLD can replace any logics funcations, even some small ASSP devices.  Base on current CPLD low price, we had studied that it can help to reduce the cost for integrate all these functions.  [2004-4-6 11:32:09]
[闂細liu-0315] Can you tell us the security of the MAX II? 
[绛旓細Elliott] Dear Sir,the security ability still be provided.and the security should be better than max3000.  [2004-4-6 11:32:30]
[闂細ecnan jing_EBY7E] CPLD鑳藉惁瀹炵幇ADC? 
[绛旓細Andy] Dear Sir,no. CPLD only provide you pure digital design.  [2004-4-6 11:34:44]
[闂細ljh9197] 濡備綍璁㎝PII鏀寔鏂扮殑鍣ㄤ欢锛� 
[绛旓細Elliott] Dear Sir,MaxII is used with QuartusII4.0.  [2004-4-6 11:38:15]
[闂細chengates] MAX II CPLDs 鏄惁鍙伐浣滃湪5v鐨勪粙闈� 
[绛旓細Susan] Yes.  But it requires extra circuit to do it.  We will provide the application note for it.  T  [2004-4-6 11:40:50]
[涓绘寔浜猴細ChinaECNet] 鐝惧湪搴ц珖鍗冲皣绲愭潫銆傛杩庡悇浣嶅～瀵窔涓婂骇璜囬爜闈㈢殑鍟忓嵎瑾挎煡锛屼甫璜嬩簬鏄庡ぉ涓崍12榛炰互鍓嶆彁浜ゃ€傛湰娆� Ipad 鎶界崕灏囧緸濉閬庡晱鍗风殑宸ョ▼甯腑鎶藉彇锛岃瑵璎濄€�  [2004-4-6 11:41:23]
[闂細tjshen] 璇烽棶EPM7128鐨勫崟浠锋槸澶氬皯锛熸槸鍚︽湁鏇翠綆浠风殑绫讳技鑺墖锛烻MT姣斿悓鍨嬭姱鐗囦究瀹滃灏戯紵 
[绛旓細Susan] You will contact you to provide more detail information.  MAX II family will be the better solution for your new design, also it will save your cost.  [2004-4-6 11:41:56]
[闂細mi040606] How many hardware and software in Altera development platform? 
[绛旓細Susan] For devices, we have MAX, Cyclone, Stratix, Stratix II famlies.Also we have NIOS, and IP.For all products are suuport by Altera software - Quaratus II.  [2004-4-6 11:44:34]
[闂細liu-0315] Where can I get the samples of MAX II? 
[绛旓細Susan] Please contact our distributors.  [2004-4-6 11:45:16]
[闂細evins] Is MAXII  must  collocate flash to replace Altera configure devices ? ex: EPC2 
[绛旓細Susan] MAX II is single chip solution, it does not need extra memory device.  [2004-4-6 11:46:17]
[涓绘寔浜猴細ChinaECNet] 鏈绶氫笂搴ц珖绲愭潫寰岋紝涓浕缍插皣璜婣ltera鍏徃鐨勫皥瀹剁辜绾岀瓟寰╂墍鏈夌殑渚嗚嚜鍚勪綅鑱界溇锛堢恫鍙嬶級鐨勬彁鍟忥紝鐒跺緦鏁寸悊涓婅級鍒颁腑闆荤恫缍茬珯涓婏紝浠ヤ究澶у鏌ラ柋銆�  [2004-4-6 11:47:19]
[涓绘寔浜猴細ChinaECNet] 鍦ㄦ锛屼腑闆荤恫鐗瑰垾鎰熻瑵绲︿簣鏈涓浕缍茬窔涓婂骇璜囧法澶ф敮鎸佺殑Altera鍏徃锛岀壒鍒ユ劅璎濆皥闁€绶氫笂鍥炵瓟鍚勪綅鑱界溇锛堢恫鍙嬶級鎻愬晱鐨凙ltera鍏徃鐨勫悇浣嶅皥瀹跺€戯紝鐗瑰垾鎰熻瑵鍚勪綅鑱界溇锛堢恫鍙嬶級绌嶆サ鐔辨儏鐨勫弮鑸囥€�  [2004-4-6 11:47:35]
[涓绘寔浜猴細ChinaECNet] 绁濆ぇ瀹朵簨妤湁鎴愩€佺敓娲绘剦蹇紒姝¤繋澶氭彁瀵惰泊鎰忚锛屾杩庨棞娉ㄤ腑闆荤恫锛屼笅娆″啀瑕嬨€�  [2004-4-6 11:47:42]

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