在线座谈

热门关键字: C接口 ELD ECL DDE 

关于本次座谈

座谈简介

参加这次在线座谈会,您将会学到如何使用通过系统集成降低整个成本,如何采用FPGA最大限度地降低风险,如何采用FPGA替代ASIC来缩短产品走向市场的时间以及采用低成本Cyclone II FPGA代替ASIC和ASSP所带来的种种好处.

精彩问答

主题:取代ASIC 设计好选择：使用新型低成本FPGA进行系统集成
在线问答:
[问：kensom] FPGA 的速度能否比得上ASIC，另外请指教哪几款FPGA的性价比最高？ 
[答：Susan] It depends on the design.  Some of design that FPGA can perform well but some of them probably ASIC performs better.   Stratix is our high performace family.  But it still depends on your design.  Please contact our distributors for further discussion.  [2004-11-11 10:32:38]
[问：liuliuyyf] 1。cyclone II 的平均价位在什么水平，例如EP2C5要多少钱。 2。NIOS 内嵌处理器都包含那些处理功能，可以和一般单片机比较吗？ 
[答：Susan] Please will ask our distributors to provide the pricing information to you.     [2004-11-11 10:34:03]
[问：wangzhuyinghn] 我在用altera公司的提供的Maxplus和Quartus软件开发产品时，用的是Verilog HDL,但该两种软件对于Verilog中的很多语句的编译不支持，特别是有关延时方面的，请问贵公司对此有何特殊的解决办法。 
[答：Stone] 目前,Maxplus和Quartus软件对Verilog 编译支持很好.有关延时方面的语句只能用于仿真,不可综合  [2004-11-11 10:35:29]
[问：dongxiongjie] 常用FPGA设计的软件有那些？各自有和优点？ 怎样选用元器件？选用元器件有何规则？ 在嵌入系统和DSP系统中该如何叫好的应用FPGA进行设计  
[答：Jerry] Altera QII, MP2可以帮助客户完成从输入，编译综合，布局布线，仿真，下载全套设计流程。也可以跟常见第三方EDA工具交互使用。如：synplify, modelsim 等。  [2004-11-11 10:39:10]
[问：asaa] 你好：我想用FPGA坐一个图形控制器（2048X2048）或 （1600X1200），用哪种芯片性价比较好一些呢，Cyclone ？CycloneII？ Stratix ？相同规模的情况下，哪种芯片较经济一些， 
[答：Robin] For your application,I think cyclone II is good choice.Other side,if you need more hipe formance image process,you can take a consider of StratixII.  [2004-11-11 10:41:24]
[问：limberm] 使用fpga中常遇到的是寄存器不足的问题，请问如何最大限度的节约寄存器资源，或者最大限度的使用寄存器？谢谢！ 
[答：Edgar] If you"re referring to register (寄存器), it is rarely the case that FPGA do not have enough registers because each Logic Element (LE) has at least one register for implementing RTL (register-transfer-level) design.  If register is really not enough for your design, usually, that"s mean you"ll have to choose a higher desity device.  However, if you"re referring to RAM (存储器), then, it is true that sometimes it is not enough, and usually what you can do is to use double-clocking multiplex techniques (时分复用)to share a single pieces of RAM.  For example, Altera Quartus"s software provide the FIFO sharing function in the Megawizard, where customer can use this function to use one piece of RAM to implement several pieces of FIFO.  [2004-11-11 10:42:53]
[问：guanghui] 请问Cyclone II的DSP板和SOPC板什么时候能够买到？ 
[答：Jerry] 根据altera schedule, CycloneII 的器件基本上在05年Q2前所有型号都可以出来，相应的DEMO板，也应该在05年Q2前都有。详细下单情况可以咨询www.cytech.com 或各地办事处。  [2004-11-11 10:44:12]
[问：gaozg] 您好！我现在使用的是altera公司stratix系列的nios开发板，我的问题是nios处理器响应中断的时间是不是比较长，时钟频率50MHz时，需要多长时间才能响应一个中断？谢谢！ 
[答：Jerry] 是这样的。nios2减少了中断数量，可能要好些。  [2004-11-11 10:45:18]
[问：xly6] 我用EPM3128，我在（分配引脚前）编译的时候看到只使用了102个宏单元，但分配引脚后编译就不能通过。请问：在实际用CPLD设计时，使用总容量的百分之多少合适？ 
[答：Stone] 一般来说,两个80%.逻辑80%,I/O 80%b比较好. 不过,你的问题不是逻辑使用过多,而是I/O分配不太合理. MAXII CPLD具备比传统CPLD更好的布通率.  [2004-11-11 10:50:20]
[问：jean_hz] 请问如果用NIOS核的话，需要哪家操作系统以及开发环境的支持？   
[答：Stone] 开发环境和软件:SOPC BUILDER,ALTERA 公司提供  [2004-11-11 10:51:29]
[问：gsdiscover] 我在什么情况下选择FPGA,或选择CPLD  
[答：Robin] Base your detail requirment.As general compare,you can implement more complex and more high performance design in FPGA,and sample design in CPLD.Other side,for your detail project,how about your directly contact with FAE for evaluation and help select device.  [2004-11-11 10:51:38]
[问：zerochina] 能否提供新型低成本FPGA的低价格开发工具套件,及免费的开发软件? 其嵌入FPGA内的noisII操作系统的性能如何?比其它的32位的单片处理器有何异同? 
[答：Edgar] Yes.  Our web-editon Quartus II software is free and it can be downloaded from https://www.altera.com/support/software /download/altera_design/quartus_we/dnl-quartus_we.jsp This version fully support Cyclone II. NIOS II/s (standard variant) can have comparable performance with ARM7 and NiosII/f would be faster.   [2004-11-11 10:52:14]
[问：l.wu] 1.请问Cyclone II 与以前的Cyclone有何区别?有那些可方便获取的开发工具?工具和可能用到的库成本是多少? 2.能否介绍一下,如果应用于数字电视视频流处理上,例如解扰变换,是否够用?需要注意些什么? 谢谢~~! :) 
[答：Jerry] 1。cycloneII 90nm的新的架构的器件。相对cyclone ,整个LE 的架构也改变了，ALM结构比LE更优秀，更大的密度，I/O, DSP模块，PLL数量，IO电平标准等。QII5.0 开始可以支持cycloneII 开发。 2。年底出的2c70 , 2c35 等容量非常大，应该没有问题。详细可以了解www.altera.com 上有关HDTV,STV等的应用网页。Altera 有比竞争对手跟积极和完善的数字电视传输设备等应用专题。  [2004-11-11 10:53:19]
[问：RemyMartin] Cyclone II什么时候可以上市？我是指EP2C35F672C6 
[答：Stone] Engineering samples of the first member of the Cyclone II device family, the EP2C35 device, will be available in February 2005, with the remaining family members rolling out in the next six months   [2004-11-11 10:55:34]
[问：xly6] 为什么不在CPLD/FPGA内部加振荡电路，比如象单片机那样，外加一个晶振和2个电容就可以提供时钟了，那样不是更方便吗 
[答：Jerry] 外加一个晶振和2个电容就可以提供时钟了。 谁说不能外接OSC? 可以提问到www.altera.com ; mysupport.   [2004-11-11 10:56:12]
[问：asaa] 题外话：若我用您们的NIOSII评估板进行网络数据传数据，最大速度能到多少呢？（用SMCC的芯片91C911），你们能介绍一些你们评估板的极限参数吗，这样我们设计时可以参考 谢谢  
[答：Edgar] 100Mbps.  For 评估板的极限参数, please refer to http://www.altera.com/support/ip/processors /nios2/ips-nios2_support.html And if you have any specific questions on any one 参数, feel free to contact mysupport.altera.com   [2004-11-11 10:56:15]
[问：__sand] 请问：通过QuartusII仿真后的程序下载到器件中后和仿真效果一致性有多高？ 
[答：Jerry] altera 的时序仿真结果跟实际非常接近。  [2004-11-11 10:57:56]
[问：pepperworm] cyclone 2需要专用的语言开发吗？  
[答：Edgar] VHDL, or Verilog Hardware Description Language. Or you can use Schematic in Quartus II (our 开发工具) Or you can use our 开发 software DSP Builder, SOPC Builder.  [2004-11-11 10:58:53]
[问：liuyonghe] 介绍一下STRATIX和CYCLONE的区别? 
[答：Susan] Startix is our high performace FPGA family.  It has greater density range and more features like build in DSP block etc.  Cyclone is low cost FPGA  which adress mid range of density.  It is cost effective solution.  For detail spec comparison, please go to www.altera.com or send a request information to sopcworldasia@altera.com.  Thanks.  [2004-11-11 10:58:54]
[问：ssufn] 是不是所有FPGA的管脚都有一对MOS管？ 
[答：Robin] In Cyclone II,here are three dedicated registers per I/O element (IOE): one input register, one output register, and one output-enable register.  [2004-11-11 11:00:17]
[问：jxyangjp] 用CYCLONE集成的32BIT处理器和ARM系列有何优势和缺点,能跑多快 
[答：Jerry] NIOS2 的fast core 在cycloneII中可以达到150DMIPS。 NIOS2 软核的优势是灵活，低成本。缺点是现在大陆地区还需要培养用户掌握这个开发开发流程。  [2004-11-11 11:01:20]
[问：kennypan] does  Cyclone II support migration to HardCopy? structured ASICs?  
[答：Susan] Currently we do not have solution for migration of Cyclone II to Hardcopy.  The reason is the pricing of Cyclone II is very competitive and most of products can use it for prodcution.  We only support Stratix families to migrate to HardCopy now.  [2004-11-11 11:01:30]
[问：DirectCG] 一般来说,同样集成度的ASIC和FPGA,在成品率和生产成本上有何差别? 
[答：Horace] Although the average selling price of FPGA devices is typically higher than that of ASICs ( around 30% ), when comparing the two solutions, carefully consider the total cost of ownership: 1. NRE Costs: ASIC costs will be much higher than when using FPGA devices. 2. Engineering Resources: Implementing a design in an ASIC requires significant customer engineering talent and resources, adding additional NRE costs. 3. Opportunity Cost: Because of the long lead times associated with ASIC development, using FPGA devices may represent a significant advantage over ASICs, allowing the customer to get to market much more quickly. 4. Lower Risk: FPGA devices offer lower risk than an ASIC implementation, as the designs used for FPGA are already proven in the target system.  [2004-11-11 11:03:39]
[问：riple] 请问工程师，cyclone 内部的pll怎样使用，使用中有什么注意事项 
[答：Robin] You can use megawizard to use PLL in cyclone.and in this PLL megawizard,you can set PLL parameter to implete your clock multiplication and division, phase shifting, programmable duty cycle, and external clock outputs, allowing system-level clock management and skew control  [2004-11-11 11:03:44]
[问：gaomin] 请告诉我用fpga设计时序电路的最好方法，怎样最大限度的避免毛刺的产生和怎样最大限度的减少延时。 
[答：Jing] 其实如果采用同步设计的话，就可避免毛刺。当然这实在时序满足的情况下而言。要满足时序，基本要考虑两方面：1。逻辑级数；2。时钟域切换处利；3。逻辑优化。4。布局布线。关于第一二点，有很多要注意的地方，例如状态机风格，If/Else或Case语句的处理，FIFO设计，算法等等。在这里不能一一详举，可参照市面有关设计风格的参考书。这里另附上一个不错的网站以供参考：http://www.sunburst-design.com/papers/ 至于后两点，是需要熟悉对逻辑分析和布局布线工具的使用。这可以和我们的技术支持联系。www.mysupport.altera.com  [2004-11-11 11:04:12]
[问：DirectCG] 在FPGA中如何实现MCU？如何操作MCU内核？ 
[答：Jerry] 如果你是把一个8051的ip放进PGA中，这个不是我们说的nios. 关于NIOS or 升级的NIOS2 有一整套开发的流程。详细了解www.altera.com/nios 页面或各地代理。  [2004-11-11 11:04:23]
[问：jean_hz] 你好，我以前用过arm9和PowerPC的处理器，但是对NIOS还不了解，我想了解一下大概的情况，比如说它支持什么样的操作系统？ 支持LINUX吗？ 有比较成熟的开发环境吗？ 谢谢！！ 
[答：Edgar] Yes.  NIOS II is a 32-bit RISC process base on Harvard Architecture (with separate data and instruction cache).  Designed for use in our FPGA, you can choose any type of peripherals you wanted to achieve your customized CPU, whose flexibilities are unmatched by pre-build CPU like arm or PPC.  We provide 成熟的 The Nios II IDE based on the open, extensible Eclipse IDE project and the Eclipse C/C++ Development Tools (CDT) Project. www.eclipse.org.  And support uCLINUX (www.uclinux.org)   [2004-11-11 11:05:27]
[问：ciber] FPGA在数字信号处理方面的能力不算强，而我们所使用的很多ASIC都是DSP+MCU形式的，这样的ASIC能够完全被FPGA所取代吗？ 
[答：Susan] It depends on your design.  Not all DSP+MCU can replace by FPGA, but some of them can.  Cyclone II has build in multiplexers that can support DSP function.  Also MCU can replace by NIOS II. For further discussion for your specific design, please contact our distributors and send an email to sopcworldasia@altera.com  [2004-11-11 11:06:07]
[问：chunsen] 在设计和验证上,FPGA和ASIC有何优缺点? 
[答：Stone] 设计上,FPGA具有更强的灵活性 验证上,FPGA更快方便.可以方便地用software 和hardware验证  [2004-11-11 11:08:46]
[问：Nigeria2004] Cyclone II主要适合应用于那些领域 
[答：Susan] Cyclone II is very suitable for Digital Consumer designs because of it competitive pricing.  Also it is good for Communication, Industrial, Computer & Storage designs.  [2004-11-11 11:09:36]
[问：riello] 能否详细介绍Cyclone II的开发软件和开发环境? 
[答：Jerry] 如果用过altera QuartusII, CycloneII的开发流程和环境因该没有问题。只不过cycloneII的支持需要QII5.0以上的版本。  [2004-11-11 11:10:53]
[问：zero] 我用DSP BUILDER设计了一个FFT器件，能把它直接通过用户逻辑放到NIOS 处理器结构中吗，如能怎么做 
[答：Robin] NIOS is soft cpu implement in Altera FPGA.You use the NIOS CPU to do FFT, and at same time you also use FPGA logic to implement FFT get more high performance.  [2004-11-11 11:11:45]
[问：ar_zhe] 我在使用quartusII的过程中，在user logic 方面遇到了问题。怎样将自己设计的模块挂接在Avelon总线上，我查看资料，有一个寄存器的文件register.v我始终不知如何去写，不知能否告知到何处去找这方面的详细点的资料或例子？谢谢 
[答：Stone] 可以参考NIOS开发资料.有具体问题可以先与骏龙公司联系,他们可以提供详细点的资料或例子  [2004-11-11 11:13:01]
[问：xly6] NOIS II中有普通的8051内亥吗？ 
[答：Robin] You can implement 8051 core into Cyclone II. NIOS II is altera latest 32 bit RISC soft cpu.  [2004-11-11 11:15:22]
[问：shicong] 我想问一下，fpga对dsp处理支持的情况，它速度和处理能力是否能与专用DSP芯片相比较，在设计DSP方面有什么优势？ 
[答：Horace] Altera Stratix II devices are the industry fastest FPGAs!  With support for internal clock frequency rates of up to 500 MHz and typical design performance at over 250 MHz, Stratix II devices provide designers ASICike performance with the time-saving advantages of a programmable solution. This must faster than specific DSP.  [2004-11-11 11:16:18]
[问：lty] nios2是以什么形式提供给用户的？是否提供源代码，是否允许用户自己修改？ 
[答：Stone] nios2是以IP形式提供给用户的,不提供源代码,用户自己可以配置CPU及外设.  [2004-11-11 11:16:20]
[问：boyfly] 请问altera的软件是否支持增量设计这个功能？ 
[答：Stone] 支持  [2004-11-11 11:17:51]
[问：anidea] 您好，我有一个关于Quartus的问题，在我使用该软件综合设计的过程中发现，对于状态机的处理，将无用的状态有化掉了，比如对于一个vhdl语言描述的双进程状态机，其case 语句中的others 部分被优化掉了，这样如何保证状态机在出错状态下的恢复？ 
[答：Jing] 这问题没有具体代码，很难在这里回答。但如果想您所说是无用的状态，而被优化掉则是正常的。可能要检查一下代码，是否忽略了一些条件。如果是涉及恢复状态的逻辑，这是不应被优化掉的。不过“others"语句的确是专家不建议用的语句。建议不要用“others"来屏蔽过多的译码比特，而应该在设计时用刚好的译码比特，而把不能所见的多余状态逐一列名他们的输出和下一状态。 另外可考虑用“one-hot"的译码方法，和"full case","parallel case" 等方法。这一网站有不错的建议，可供参考:http://www.sunburst-design.com/papers/  [2004-11-11 11:18:22]
[问：chunsen] 采用FPGA设计个性化系统是否意味要回到ASIC的路子上去?它和ASIC有和区别? 
[答：Edgar] FPGA vs ASIC: (FPGA has the following main advantage) -- faster time-to-market (becuase FPGA can be reprogrammed in minutes, ASIC has long design cycle) -- Lower risk (because FPGA can be verified in system immediately, while ASIC cannot be verified in system until 3-6 months away from design finish). Altera is also an ASIC prvoider and we provide a FPGA-->ASIC flow named "HardCopy" flow.  Our HardCopy is Strcuture ASIC device preserves FPGA architecture and FPGA-proven functionality.  Hence it combine the benefit of both FPGA (flexible, low cost, low risk) and ASIC (lower cost), and HardCopy has the added benefit of faster turn-around-time than traditional ASIC because it preserves FPGA architecture and take less time to manufacture. For more information about HardCopy, please refer to http://www.altera.com/products /devices/hardcopy/hrd-index.html [2004-11-11 11:20:52]
[问：riello] 软处理器Nios II目前的速度能动达到多少?性能达到什么样的水平? 
[答：Edgar] Nios II can achieve performance over 200 DMIPs.  Feel free to refer to http://www.altera.com/products/ip /processors/nios2/ni2-index.html   [2004-11-11 11:22:38]
[问：youbaoshan] nios 2 如何配置引导程序？ 
[答：Jerry] NIOS2 中一个重要的区别是去掉了bootrom 程序，这一点不同于Nios了。详细可以download 或向各地office索取有关nios2 training的文档中有详细介绍。  [2004-11-11 11:23:35]
[问：zzkeng] 如何对FPGA的配置文件加密？ 
[答：Jing] 目前，我们的Stratix-II器件支持配置文件加密。基本上是由QuartusII来加密，并由Altera提供特有密钥的Stratix-II芯片来配合使用。每一客户的密钥都不同，所以就算别人偷取了贵公司的加密配置文件，也不能再同型号的芯片上使用。  [2004-11-11 11:26:16]
[问：陈炜] EPM7128S系列I/O驱动能力有多少mA 
[答：Jerry] LVTTL,LVCOM 的驱动能力不一样，7128S也是一款很早的cpld. 其IO驱动不可以调整。一般在12mA左右.建议你在数据手册的上查找driver ability. cyclone或新的MAX II CPLD 其驱动都可以调整。不同的电平标准从2mA ,4mA, 8mA 12mA 20mA 等。  [2004-11-11 11:29:03]
[问：theprimegod] 请问fpga的功耗一般有多大？对于便携式系统是否适用？ 
[答：Stone] fpga的功耗一般比ASIC大,主要取决于你设计的资源使用情况,时钟工作频率,I/O使用等因素.  [2004-11-11 11:29:09]
[问：zzkeng] 在速度和保密性能上,低成本FPGA是否完全胜过ASIC,到了能完全取代ASIC的地步? 
[答：Susan] For speed and security features, low Cost FPGA can replace most of ASIC designs but not all of them.  It depends on your designs.  For furture discussion on your specific design, please contact our distributors or send an email to sopcworldasia@altera.com  [2004-11-11 11:30:28]
[问：josephfu] 如果我在开发中需要您们的技术帮助，请问我可以联系的方式？我在深圳。  
[答：Jing] Please email inquiry@cytech.com, 或是将问题发到www.mysupport.altera.com.  [2004-11-11 11:31:56]
[问：maszcy] 用Cyclon实现1024点浮点FFT需化费多少时间? 
[答：Jerry] 1k 点浮点FFT可以download FFT IP userguider 查询。cycloneII中有专用硬DSP 乘加器。cyclone 没有，所以情况不一样。   [2004-11-11 11:33:51]
[问：DirectCG] 在设计的灵活性和功耗上,ASIC和FPGA有何差异? 
[答：Edgar] FPGA has the following benefit compare to traditional ASIC: 1.  Faster time-to-market (FPGA can be reprogrammed and verified in system minutes after design finsh, while traditional ASIC has longer designer cycle) 2.  Flexibility--FPGA is reprogrammable.  ASIC cannot. 3.  Lower risk--FPGA can be verified in system right after design finish.  ASIC cannot as you have to wait until the silicon come back after a long manufacturing period (3-6 months). Altera is a also an ASIC vendor.  Altera provide FPGA --> ASIC flow named the "HardCopy" flow.  Our HardCopy devices preserves FPGA architecture and FPGA-proven functionality, and take less time to manufacture than traditional ASIC.  Hence, "HardCopy" combine benefits of both world (low risk verification in FPGA, and achieve lower cost later by doing the "HardCopy" flow).  For more info, please refer to http://www.altera.com/products/devices /hardcopy/hrd-index.html   [2004-11-11 11:34:42]
[问：zzkeng] FPGA中的时钟分布和性能是否能满足ASIC的要求? 
[答：Jing] 只要时序报告显示速度满足，就没有问题。FPGA的全局时钟是可以满足零skew，和高扇出的要求的。  [2004-11-11 11:35:45]
[问：zzkeng] 采用低成本FPGA替代ASIC,在成本上有何优势?能举例说明或用数字说明码? 
[答：Horace] When comparing ASIC and FPGA, carefully consider the total cost of ownership: 1. NRE Costs: ASIC costs will be much higher than when using FPGA devices. 2. Engineering Resources: Implementing a design in an ASIC requires significant customer engineering talent and resources, adding additional NRE costs. 3. Opportunity Cost: Because of the long lead times associated with ASIC development, using FPGA devices may represent a significant advantage over ASICs, allowing the customer to get to market much more quickly. 4. Lower Risk: FPGA devices offer lower risk than an ASIC implementation, as the designs used for FPGA are already proven in the target system.  [2004-11-11 11:38:18]
[问：riello] 能否举例说明Cyclone如EP2C70的价格?和其它公司同类产品相比有和优势? 
[答：Susan] Compare with the same products in the market, Cyclone II has advantages at: X1.5 performace 30-50% lower cost per LE larger density (up to 68416 LE). For more detail pricing information, please contact our distributors or send your request to sopcworldasia@altera.com  [2004-11-11 11:38:59]
[问：DirectCG] 在处理功能和逻辑功能上,FPGA和ASIC有何差别? 
[答：Edgar] 在处理功能和逻辑功能上,FPGA和ASIC 基本没差别  [2004-11-11 11:39:29]
[问：beachover] nios2和nios的区别是什么 
[答：Robin] NIOS 2 is latest 32-bit soft cpu  implement in Altera FPGA. Use NIOS II,you can get more high cpu formance with less resource compare with NIOS. NIOS is 16 bit ISA RISC CPU and NIOS II is a 32 bit RSIC CPU; You also use IDE to design your CPU software. For detail difference between them,how about contact with FAE get help.  [2004-11-11 11:44:30]
[主持人：ChinaECNet] 所有问题均已提交给Altera公司的专家。座谈期间未回答的问题，Altera公司专家也会逐一回答，并在中电网上公布，请大家注意收看。  [2004-11-11 11:47:27]
[问：chunsen] 请详细介绍ASSP的概念.为什么它的客户设计成本是很低的，面市时间是很快的?如果是这样,FPGA如何和它进行竞争? 
[答：Horace] ASSP is targeted on some specific application. It mean there is no design ability needed, and all the feature is standarded ( un-changable ) However, FPGA can provide : 1.Ability to add/remove features in hardware; 2.Ability to change functions in hardware; 3.Ability to integrate several functions in a single chip (and reduce board congestion) For the price, ASSP due to no design effort need to make, and all your competitor is able to do the same what you are doing, it make your profit margin lower. However, you can use FPGA to do a specific feature product as you want. Your profit margin is also higher.  [2004-11-11 11:48:03]
[问：boyfly] 我想请教一下时序限制的方法。我用altera的芯片做设计，在板子上调测时，功能正常，稍作无关改动（如引一测试管脚）功能就不正常了，我认为是时序做的不好，你有什么好的时序限制的经验教我，谢谢你 
[答：Jerry] 这种情况一般都是客户有关键时序处在临界。我建议你详细阅读QII handbook 关于timing assignment 部分。通常我们会在assign/timing seting/ indiviul... 定义所有关键path. 然后到assignment editor /timing 中去根据不同的feature 选择关联上不同的constrain.  [2004-11-11 11:49:45]
[问：chunsen] 在FPGA设计中怎样可以使得芯片资源利用率提高？它的利用率最高可达到多高? 
[答：Jing] 这基本上可又设计软件实现。在QuartisII的Assignment Editor中的Optimization Technique logic option,选Area. 另外，Auto Packed Registers 选项可选为ON. 现在的利用率可达95%或更高。但要小心，设计太满会令编译时间非线性增加，并使后期调试工作非常困难，帮助调试的内嵌式逻辑分析仪也因此放不到器件内。  [2004-11-11 11:50:48]
[问：jinib] FPGA的发展趋势？ＶＨＤＬ与ＶＥＲＩＬＯＧ哪种编译效率更高，更通用，谁是主流？它们编译使用软件有关吗？对ＦＰＧＡ的设计，使用何种输入方法效率更高，更稳定，可靠？ 
[答：Jerry] 现在verilog 的人多些。altera 或第三方的EDA普遍都支持这两种。软件都很丰富。  [2004-11-11 11:51:34]
[问：gaozg] 刚才我问了一个关于中断的问题，如果想利用nios处理器来处理中断，而且希望有较快的响应时间，我该如何做？ 
[答：Jerry] contact: jerrypan@cytech.com  [2004-11-11 11:52:32]
[问：xly6] 请问哪儿有ALTERA元件的PROTEL的原理图库和PCB封装库下载？ 
[答：Jing] 我们只有OrCAD的symbol. 不过PROTEL是有转圜工具的。 http://www.altera.com/support/software/ download/pcb/pcb-pcb_index.html  [2004-11-11 12:01:19]
[问：jinib] 使用ＦＰＧＡ／ＣＰＬＤ的好处和主要优点体现？ 
[答：Susan] FPGA is gate arry like architecture, SRAM base, rich registors and address mid to high density range designs. CPLD is PAL like architecure, EEPRROM base, suitabe for more logic design and address in low to mid range designs.  It depends on your design to decide whether use FPGA or CPLD.  If your design is more complicated and need more registors, then FPGA is the choice.  If you just like to do the simple logic design, like decoder, the CPLD is your choice.  For more detial discussion, please contact out distributors or send an email to sopcworldasia@altera.com  [2004-11-11 12:01:38]
[问：gaofang1976] 1）这些新型低成本和通常FPGA相比有什么不同？ 2）在SOC越来越成为潮流的今天，虽然是些中低规模，但是还是涉及许多HARD MACRO在里面，怎样通过这些低成本的FPGA来达到验证的目的？ 
[答：Edgar] For 1) With advance technologies such as 90nm, advance chip architecturing ,新型低成本的Cyclone II will provide the lowest cost FPGA in the market, and faster performance than older-generation FPGA. For 2) Altera understands the pain associated with traditional ASIC design, as we are an ASIC vendor as well.  We provide the FPGAs (some of these has Hard Macro, such as CDR in our Stratix GX), development tools, intellectual property (IP), and a seamless migration path from the function-verified FPGA to high-volume production devices named the "HardCopy". Now designers using HardCopy devices can manage costs, risks, and market uncertainty.  [2004-11-11 12:03:15]
[主持人：ChinaECNet] 恭喜您，北京讯风光通信技术开发有限责任公司的boyfly经过电脑抽奖您在本次座谈中获得一部MP3播放器。请网名为boyfly的用户与中电网联系(8610-82888222-7009 或 lilin@chinaecnet.com)。  [2004-11-11 12:03:25]
[问：liuyonghe] STRATIX器件的资源有多大?一般对于其中8个BANK 怎样分配?  
[答：Robin] Straitx device is alera .13 u mass product high performance FPGA. The resource is from 10K LE to 80K LE. For some different bank,we can support different charater characteristic.For detail,you can get from stratix handbook or get information from FAE  [2004-11-11 12:05:02]
[问：maszcy] 如何估算一个开发课题在Cyclon上所占资源?从而决定选择何档次的Cyclon. 
[答：Jing] 最准确的方法是将类似的设计放到QuartusII中跑一下。让QuartusII自动选器件。  [2004-11-11 12:05:10]
非在线问答:
[问：] 1，有没有关于永磁同步电机控制采用矢量控制的IP,本人准备采用FPGA设计。<br> 2，关于FPGA的时钟输入，采用通用的有源晶振是否可以。
[答：] 1)How about got to altera web sit,entry the automotive application web page for get more information for your application.2)Yes.base your system clock requirment,you can select oscillator.
[问：] 1.请问FPGA与单片机各有何优点？ 2.我想学FPGA编程，但不知道怎么样学，是否需要一些开发工具？谢谢！！！
[答：] 1)Compile with MCU,FPGA have more high performance in some high performance application.Other side,you can also add soft cpu,like NIOS II in alera FPGA,you can get a supper system with high performance and more flexible.2)You can get some basic training document from FAE or web sit,other side,personal advice,try to do a really FPGA design,and you can get more.
[问：] 1。 cyclone I 器件是否可以实现时钟信号的倍频工作（2-4倍频）， 如果可以，如何做？（我使用verilog HDL） 2。 cyclone I 和 cyclone II如果在都能符合需求的情况下，请问曹先生您推荐使用哪一种? 有什么理由吗？
[答：] 1)Yes.You can use PLL in FPGA to implement。PLL megawizard,you can set PLL parameter to implement your clock multiplication and division, phase shifting, programmable duty cycle, and external clock outputs, allowing system-level clock management and skew control .With the megawiazard,you can get *.v file include your parameter PLL function,and they you can instance it in your high level verilog file. 2)Cyclone II is a new generation with low cost FPGA and at same time you also get more high performance.For detail type you better select,I think you have better make detail discussion with FAE.
[问：] 1\请问Cyclone2与cyclone 的区别主要在哪里，为什么是两个系列？ 2\Cyclone2的I/O接口支持哪些高速协议，最高到多少兆？
[答：] 1。cycloneII 90nm的新的架构的器件。相对cyclone ,有更高的处理性能，更大的密度，更高的I/O电平标准和速度支持, 专用的乘法器模块等。你可以从altera 网站上获得免费的web versiong 的QII 软件来开发cyclone II 器件。也可以联系代理商购买全功能板的QII 软件。<br> 2。Cyclone II Device Single-Ended and Differential I/O Standards Support ,as highlight, like Cyclone II can support DDRII ,QDRII,and LVDS high to 805Mbps(Rx)622Mbps(TX),mini-LVDS(170Mbps) etc,and you can get more information from cyclone II handbook. And you can download it from altera web sit.
[问：] altera公司推出的产品跟其他家相比，我一直认为技术支持做的比较好！我感觉这是altera在大陆销售较好的原因
[答：] Thanks for your comment, we target provide the best service to customer no matter in China or in Worldwide. You will see Altera will keep growing in future
[问：] ASIC.FPGA的全称及应用？
[答：] ASIC = application-specific integrated circuit ; FPGA =Field Programable Gate Array.In altera web site,you can find more widly FPGA system application. http://www.altera.com.cn/solutions/sln-index.html
[问：] assp是什么？
[答：] ASSP = application-specific standard products
[问：] CPLD 现在 能做到多少个门电路
[答：] Now,we use MC,LE or ALM to calculate CPLD or FPGA resource,and the "gate" concept use in ASCI as general.
[问：] Cyclone II FPGA资源丰富，但是它的某些内部资源或者IO引脚是否为复用的。比如，使用了专用的外接存储器接口电路，就不能使用高速差分I/O功能，等等。
[答：] Yes.You can use select multi function I/O as one of function to get a flexible application.But at some time,we have to trade-off flexible and performance,and for some high speed I/O application,with dedicate I/O,we can get a high and steady performance.
[问：] cyclone II 系列器件什么时候可以在中国上市，它的价格和第一代 cyclone相比是高还是低呢？谢谢
[答：] The first Cyclone II 2C35 will be release at Q1,2005.Compare with Cyclone,you can get a low cost and high performance.
[问：] cyclone 与cycloneII的最大区别是什么？
[答：] CycloneII will be more cost saving compare with Cyclone. CycloneII can Up to 68,416 LEs for high-density applications; Up to 1.1 Mbits of embedded memory for general-purpose storage; Support for single-ended I/O standards including 64-bit/66-MHz PCI and 64-bit/100-MHz PCI-X (Mode 1) protocols; 4 PLL; Dedicated external memory interface circuitry to interface with DDR2, DDR and SDR SDRAM, and QDRII SRAM memory devices............. For detail, you can refer to http://www.altera.com/products/devices/cyclone2/cy2-index.jsp
[问：] Cyclone2 系列的EP2C35F672C6价位大概在多少
[答：] For pricing issue, you can contact with local distributor
[问：] Cyclone2比Cyclone能低多少钱
[答：] Due to CycloneII is using 90nm technology. Cost will be very low. For detail, you can contact with local distributor
[问：] cycloneII具体是怎样取代ASIC的功能？其优势是?
[答：] FPGA can provide a time to market and lower cost solution to customer. You can refer to below technical note : http://www.altera.com/literature/an/an311.pdf
[问：] cycloneII是不是不需要外部配置芯片？价格多少？可应用在哪些领域？
[答：] Cyclone II is SRAM technical,and when power off,the config information will dispear.so it need config when power up.For FPGA,here are several method to config,you can select one for your detail application.and Altera also provide a low cost serial config device to config Cyclone II.
[问：] cyclone的最小功耗是多少？
[答：] Power consumption is base on selection of device and your design. Quartus II can provide the calculation function.
[问：] cyclone与cycloneII的性价比分别如何？
[答：] CycloneII will be more cost saving compare with Cyclone. CycloneII can Up to 68,416 LEs for high-density applications; Up to 1.1 Mbits of embedded memory for general-purpose storage; Support for single-ended I/O standards including 64-bit/66-MHz PCI and 64-bit/100-MHz PCI-X (Mode 1) protocols; 4 PLL; Dedicated external memory interface circuitry to interface with DDR2, DDR and SDR SDRAM, and QDRII SRAM memory devices............. For detail, you can refer to http://www.altera.com/products/devices/cyclone2/cy2-index.jsp
[问：] cyclone与fpga的区别
[答：] Cyclone is a kind of FPGA. It is a low cost Altera FPGA.
[问：] Cylone II 是否适合用作DSP算法的硬件平台？
[答：] 从一定意义上说，新的全铜线工艺的PPGA ，如cycloneII 能支持客户对更高处理速度的要求，cycloneII中含有专门的硬件乘法器，更加适合作为硬件平台来实现DSP算法。
[问：] FPGA 和DSP在未来的发展的趋势如何？
[答：] 有一种未经证实的预测将来IC行业只会剩下PLD 和模拟器件， PLD密度越来越大，价格越来越便宜，更复扎的DSP功能会有一种趋势融入PGA.
[问：] FPGA的详细应用和设计思路?
[答：] 你可以联系FAE或联系support@cytech.com得到更多应用及设计信息。
[问：] FPGA能完全取代ASIC吗？或能取代哪些类ASIC？
[答：] It will not totally replace ASIC, but will share most of the ASIC market in furture. It is because we can provide a time to market and lower cost solution to customer
[问：] fpga一般是用做asic前设计测试用么？ 如今若能取代asic设计，岂不是在将来的升级改造方面具有更大的灵活性？另外当系统集成流片之后，系统的稳定性如何？ 新型低成本FPGA购买开发版和IPcore的成本较高，如何解决！？
[答：] 1，In ASIC design,you can use FPGA to implement verify.But FPGA have a widly application except ASIC verify.2) 建议到www.altera.com 上查看详细hardcopy 的solution.
[问：] FPGA与CPLD的开发有多大区别?需要再学什么新的知识
[答：] 没有区别。只不过FPGA通常密度大于CPLD。你可以根据你的具体系统需求选择FPGA还是CPLD。
[问：] fpga与cpld的区别是什么?
[答：] 以前fpga 都是SRAM 工艺，CPLD 是EPROM工艺. 但新一代的FPGA也有flash工艺的。无需外配置rom.
[问：] how do cyclone II devices compare with cyclone devices ?
[答：] CycloneII will be more cost saving compare with Cyclone. CycloneII can Up to 68,416 LEs for high-density applications; Up to 1.1 Mbits of embedded memory for general-purpose storage; Support for single-ended I/O standards including 64-bit/66-MHz PCI and 64-bit/100-MHz PCI-X (Mode 1) protocols; 4 PLL; Dedicated external memory interface circuitry to interface with DDR2, DDR and SDR SDRAM, and QDRII SRAM memory devices............. For detail, you can refer to http://www.altera.com/products/devices/cyclone2/cy2-index.jsp
[问：] how protecting the desgin data cannot be copy illegally with low cost ?
[答：] 1。更复扎的配置方式。如cpu, cpld+flash. 2.将部分逻辑移至到一片可以加密的CPLD中，这样从FPGA的配置rom上截取的数据不是完整的设计。3.选flash工艺的fpga.无需外部rom, 或者anti-fuse 工艺的，一次编程。
[问：] If I select &quot;CYCLONE II&quot; and I want to use the sdram or DDR interface controller, May I use it free? or I must pay for it?
[答：] 正版QII 从04年8月到明年8月有一年免费附送这几个IP，无需购买。一年后，IP升级的版本不支持，但老的可以继续用。
[问：] May I ask the schedule of Cycle II?
[答：] All p/n begin release out at Q2,05. If you only need ES sample for support your design, pls contact with FAE.
[问：] nios2IDE环境中是否支持串口调试和烧写FLASH，而不用JTAG
[答：] 串口支持。JTAG时第一版BB2不行，第二版的USB的可以了.原因在于debug和signalTapII公用时有问题，所以才要改第二版本。
[问：] pll的分频似乎有限制，在pll megawizard里，不可以设置很大的分频系数，例如对时钟信号进行10分频这样的操作，不知道是否正确？
[答：] 是的。如cyclone中最小的分频》＝5/32.这是因为cyclone的最小输入时钟是15.26MHZ.stratix 可能又不一样。最小输入值不同。
[问：] Quarters 2 软件你们能免费提供吗，怎么在FPGA里面做CPU
[答：] web version 是free的。查看NIOSII的详细资料，了解altera软核CPU.
[问：] why are cyclone ii devices an ideal alternative to ASIC S ?
[答：] low cost ! 90nm process technology.
[问：] 本公司能否召开关于ＦＰＧＡ，ＣＰＬＤ专题讲座？
[答：] You can get training information from altera or distributor web site.
[问：] 除了Straix系列，那些还支持GTL ，HSTL与LVDS IO
[答：] cycloneII ,GX, stratixII
[问：] 低成本的fpga能保证性能不下降吗？
[答：] 低成本主要的贡献是工艺保证的。主要的几家pld厂商其实都是ic design house, 成本有一半是各自所选的代工厂决定。
[问：] 对于Cyclone器件上运行的NiosII系统来说，工作在超出时序报告的时钟频率会对系统的性能造成多大的隐患？举例说，现在时序报告是60M，我工作在70或者80M的时候，问题会大吗
[答：] 对器件本身没有任何损害，重要的是你功能会不稳定或不正确。
[问：] 对于Cyclone系列的FPGA应该采取怎样的加密方式呢
[答：] 所有sram架构的不能独立加密。除非flash工艺或anti-fuse.，所有的补救都是把加载弄的更复扎。如CPU加载，CPLD 加载等。但新的stratixII 加有专门的DES电路，永保无忧。
[问：] 对于器件上的选择，您有什么看法？
[答：] 性能价格，服务支持。产品未来周期等。
[问：] 仿真时钟频率同实际下到开发板上能正确运行的时钟频率会有很大差距吗？
[答：] altera 时序仿真基本一至。
[问：] 该新型fpga市场价一般有几个价位?
[答：] For pricing issue, you can contact with local distributor
[问：] 各位老师，你们好！我是一名电子工程师，没有什么软件基础，对硬件描述语言（VHDL）很感兴趣。请问那有开发软件环境买？怎样才比较容易上手。是不是必须要C基础才行？谢谢！
[答：] You can use Quartus II to design your system.and you can download free web verion from altera websit,or contact with distributor for get full version QII.As personal advice,Verilgo is more general used and easy start your basic design.
[问：] 关于cyclone系列的PLL？PLL的三种反馈组态具体，normal mode、Zero Delay Buffer Mode、No Compensation不是很明白？PLL的供电电源VCCA_PLL的处理Partitioned VCCA Island within VCCINT Plane怎么样将VCCA_PLL隔离开来？PLL可以实现占空比的可调，在实际应用中有什么意义呢，请举例？
[答：] 1)In normal mode, the PLL phase aligns the input reference clock with the clock signal at the ports of the registers in the logic array or the IOE to compensate for the internal global clock network delay.2) The clock signal on the PLL external clock output pin (PLL[2..1]_OUT) is phase-aligned with the PLL input clock for zero delay 3)In this mode, the PLL does not compensate for any clock networks, which leads to better jitter performance because the clock feedback into the PFD does not pass through as much circuitry.4) You can get detail information from cyclone hand book "PLL" part.5)For power design when you use FPGA,pls take a reference with end of very device handbook.
[问：] 贵公司的DPLL core要多少钱？
[答：] How about directly contact distributor for get detail IP you need and price.
[问：] 贵公司有没有逻辑多，引脚少的芯片？什么系列，型号是什么？
[答：] How about directly contact distributor for get detail device type select and price.
[问：] 贵公司有没有提供廉价的FPGA和 CPLD的开发套件，价格大约在多少
[答：] Yes, you can select the development tools in below website : http://www.altera.com/products/devkits/kit-dev_platforms.jsp
[问：] 何为ASSP?英文全称? 何为90nm工艺? 何为DMips?英文全称? Altera如何发音?
[答：] 1)ASSP = application-specific standard products ; 2)90nm Technology, you can refer to http://www.altera.com/products/devices/cyclone2/features/tsmc/cy2-tsmc.html 3)MIPS是指一个CPU可以在一秒钟执行多少百万条的指令。如果MIPS是50，就是说这个CPU在一秒钟可以执行50个百万条的指令。DMIPS是指Dhrystone MIPS.。用CPU来运行一个标准的测试程序，从而推算出的一个数值用来衡量CPU性能 。
[问：] 可以提供QUARTUS2 软件吗
[答：] You can download free QII in altera web sit, or you can contact with distributor to get full version QII.
[问：] 你好！请问用EPM7128设计DPLL宏单元够用吗？不用带锁相环的是因为会增加产品成本
[答：] You can select low cost FPGA with PLL or altera low cost CPLD:MAX II to implement your application.
[问：] 你们能够提供一些FPGA产品资料通过电子邮件给我吗？
[答：] You can register in Altera web site : http://www.altera.com/corporate/contact/signup/con-signup.jsp
[问：] 您好！我是个菜鸟！我想问的是：最近听有的人说可以不用MODELSIM做仿真，直接用CHIPSCOPE看.MODELSIM用作教学是比较好，可是还是不如CHIPSOCPE.而且我还想知道，在ISE中直接调用MODELSIM的方针结果，和在MODELSIM的环境下直接做仿真，两者之间有什么区别？
[答：] 1)I think you have make a confusion.With Modelsiim,you can make function or timing simulation before board level simulaiton.and help you early make sure your design and debug your design.2)Altera provide a integrated develop software:Quartus II to support you design your system.and you can use Signal tap II to directly get data from internal logic by Jtag. and it is a good tools for your system board level debug.
[问：] 您好！我需要设计三组（每组三个）三相移位脉冲，作为CCD47-20的逻辑驱动脉冲，每组的周期都不一样，请问用什么方法设计比较好？另外，我需要比较详细的介绍VHDL语言的中文资料及逻辑设计例程，请问哪里可以下载
[答：] How about discuss FAE for your detail application.
[问：] 您好，您能详细谈一下该型FPGA的优势吗？
[答：] 1. Very Low Price -- 90-nm technology 2. Excellent Feature -- Up to 68,416 LEs for high-density applications; Up to 1.1 Mbits of embedded memory for general-purpose storage; Support for single-ended I/O standards including 64-bit/66-MHz PCI and 64-bit/100-MHz PCI-X (Mode 1) protocols; 4 PLL; Dedicated external memory interface circuitry to interface with DDR2, DDR and SDR SDRAM, and QDRII SRAM memory devices............. For detail, you can refer to http://www.altera.com/products/devices/cyclone2/cy2-index.jsp
[问：] 您好，我想用FPGA做一种图像压缩芯片，大约1M左右等效门，内含128k以上RAM或ROM，且RAM或ROM可以分为16块以上（具有独立数据地址线）。
[答：] How about discuss FAE for your detail application.Other side,we have some image compression application solution in Altera FPAG.You also get more information from altera web sit system application,image process page or get information from altera image process IP page.
[问：] 您好，我使用了megawizard，可是发现m、n的值似乎并不能按照1～32之间随意改动，出现“cannot implement the requested pll”的错误，并且指明原因是“Post divider max count exceeded”，请问这是怎么回事？
[答：] Here is equivalent formula,for example,you use PLL to generate a internal clock: fC0 = fVCO/G0 = fIN × (M/(N × G0)),so fVCO=fC0*G0,if fC0*G0>fVCO(Max) or fC0*G0<fVCO(Min),here will display:Post divider max count exceeded.
[问：] 您好，我想用您们的STRATIX 2 FPGA开发一款支持DDR2接口的设备，请问目前能支持DDR的最高的速率是多少？
[答：] DDR 400Mbps DDR2 533Mbps
[问：] 您现在主要是在用什么语言写程序,VHDL,VERILOG,还是SYSTEM C?有的人说单片机的时代就要过去了，您是怎么看待汇编语言和AISC,FPGA的相关编程语言之间的区别和联系的?
[答：] 现在一般采用VHDL,VERILOG进行PLD设计.汇编语言主要是针对CPU的低级编程语言,不适合ASIC/FPGA设计.
[问：] 请问，Cyclone II 器件的性能和价格与Cyclone相比有何优势？能举例说明EP1C3和EP2C5的性能和价格特点吗？
[答：] 1. Very Low Price -- 90-nm technology 2. Excellent Feature -- Up to 68,416 LEs for high-density applications; Up to 1.1 Mbits of embedded memory for general-purpose storage; Support for single-ended I/O standards including 64-bit/66-MHz PCI and 64-bit/100-MHz PCI-X (Mode 1) protocols; 4 PLL; Dedicated external memory interface circuitry to interface with DDR2, DDR and SDR SDRAM, and QDRII SRAM memory devices............. For detail, you can refer to http://www.altera.com/products/devices/cyclone2/cy2-index.jsp
[问：] 请问，FPGA比ASIC，具体有哪些方面的优点？
[答：] 1. Pricing ; 2. Time to market ; For detail, you can refer to http://www.altera.com/products/devices/cost/cst-cost_step1.jsp
[问：] 请问,FPGA与CPLD有何差别?各自的优点和缺点?发展前景?是否FPAG会取代CPLD?FPGA的选择依据及优劣标准?FPGA与CPLD在编程和使用上有何差别?FPGA/CPLD的宏单元大小与设计内容的多少如何估算?比如,一个宏单元能容纳多少个双输入逻辑与门或三输入逻辑与门?在设计内容过大时如何优化?
[答：] FPGA一般容量较大,内嵌RAM,传统FPGA一般采用SRAM工艺,LUT结构.需要配置芯片.CPLD一般逻辑容量较小,采用EEPROM或FLASH工艺,非易失,P-TERM结构,单片,Altera推出的MAXII CPLD将FPGA的结构与CPLD的单片,非易失相结合.一般来说,一个宏单元可以等价于30个左右的双输入逻辑与门.
[问：] 请问,对于fpga其保密性能否得到保障了?!
[答：] Altera的StratixII具有了保密功能,以前的FPGA可以通过CPU/CPLD对其加密,可以联系骏龙公司技术支持.
[问：] 请问，我有个笔记本上面没有lpt口，现在编程都是通过台式机完成的，能有什么解决方法没有。先前买了usb转lpt的转接线没有作用
[答：] 可以使用USB口的USB-Blaster或串口的Masterblaster
[问：] 请问：Altera公司有低功耗的CPLD产品吗？
[答：] Yes, our MAXII is low power consumption; you can refer to http://www.altera.com/literature/br/br_max2.pdf
[问：] 请问：设计中既有严格的逻辑控制，又有一些简单的时序控制，需要64Kbit存储单元，是FPGA适用还是CPLD好？些？
[答：] FPGA适用,FPGA逻辑资源多,寄存器资源丰富,内嵌Memory
[问：] 请问Altera公司如何看待中国的消费市场领域？
[答：] Altera had started business in China for a long time. We have built up the local team ( local Sales, Technical supporting, Distributor ). As China is a major consumer product manufacturer, we are keeping development our product to fit into different market segment. We forecast consumer electronics will grow very fast in China.
[问：] 请问altera芯片，稍改动后，从新布局布线后差别较大，有什么好的办法
[答：] 可以使用Logiclock或Increment Fitting
[问：] 请问Cyclone II 在功耗方面有何优势？一般情况下的上电时电流有多大？ 多谢
[答：] This specification will be available in a future version of the data sheet.
[问：] 请问cyclone系列芯片的上电电流为什么那么大？EP1C6有500mA，那么给它的供应电源电流应该大于500mA，是这样的吗？关于上电电流为什么这么大？请详细讲解一下
[答：] EP1C6的供应电源电流设计应该大于500mA,主要跟半导体工艺有关,FPGA一般都有一个比较大的涌电流
[问：] 请问DSP BUILDER 3.0和2.2 有什么区别
[答：] DSP BUILDER now released version is 2.2
[问：] 请问fpga的功耗一般有多大？对于便携式系统是否适用？
[答：] FPGA功耗与工作频率,I/O使用及资源等使用情况有关,Altera有CycloneII功耗计算的表格,能否用于便携式系统,可根据估算结果及供电情况来判断.
[问：] 请问maxplus II 开发套件 是否可以与quartusII 开发软件 转换？
[答：] You can switch your design in Maxpuls II to Quartus II,and altera provide a friendly interface help you seamless migration with low risk and easy.
[问：] 请问QII5.0什么时候推出？
[答：] We do not know next version of Quartus II is called 5.0 or 4.xx ; so we cannot define when will release. But Altera design software tools is always in development and improving. For the roadmap, you can refer to http://www.altera.com/corporate/about_us/roadmap/abt-product_roadmap.html
[问：] 请问工程师，cyclone器件手册中标明的dsp block和multiplier只见有什么异同，具体数值之间有什么对应关系。谢谢
[答：] cyclone II器件中的每一个dsp block can be configured to support one 18 × 18 multiplier or two 9 × 9 multipliers.
[问：] 请问目前国内有没有新型低成本FPGA进行系统集成使用的成功安例，作为老的ASIC 设计，新型低成本FPGA设计在那些方面有所改进呢？
[答：] 1)For system FPGA solution,pls take reference with altera web sit, http://www.altera.com.cn/solutions/sln-index.html 2)Compare with ASIC,FPGA is more time to market,flexible.
[问：] 请问能否用基于Cyclone的软DSP代替现有的DSP硬件芯片?二者相比,Cyclone自己的优势是什么?有没有什么缺点?
[答：] 不能完全用Cyclone II的DSP代替现有的DSP硬件芯片,Cyclone优势数学运算用并行硬件实现速度快,但不能完全代替DSP处理器.
[问：] 请问现在可以买到Stratix II High-Speed Development Board 吗？
[答：] Yes, pls refer to http://www.altera.com/products/devkits/altera/kit-hs-2S60.html and contact with distributor to get the board.
[问：] 请问一下cycloneII和stratix在性能上有什么区别，性价比那个更好一些？
[答：] Cyclone II is targeted on low cost FPGA solution; While Stratix is targeted on High preformance solution. Both Price/performance ratio is higher than our competitor.
[问：] 请问专家:cyclone所集成的嵌入式系统相对ARM系统有何优势和缺陷
[答：] 1)Custom Microcontroller/Custom Instruction/Custom Interface 2)Integration of Processor & Programmable Logic 3)State Machine Replacement
[问：] 请专家提供详尽的FPGA开发流程或具体方案。
[答：] You can get detail information from QII on line help or QII hand book.or you can contact with FAE to discuss detail .

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