| 主题：高性能时钟: 解密抖动 |
| 在线问答： |
| [问：jimmy88531] |
何谓亚皮秒抖动？这种时钟的电磁兼容性怎么样？ |
| [答：Jing] |
Sub-Picosecond means the time jitter less than 1X10E-15 second. Since
it"s very little jitter ,it"s not apt to affect by EMC. But EMC performance
will be also derived from other factors. |
[2005-10-12 10:51:51] |
| [问：shmm2002] |
AD9510的时钟抖动最小能做到多少？ |
| [答：Wenshuai] |
When in LVPECL output, it can be 130ps. Please refer to the datasheet
of AD9510. |
[2005-10-12 10:53:30] |
| [问：luogongqiang] |
测量时钟的抖动有直接测量和间接测量方法,那种较容易实现和精度高些? |
| [答：Ted] |
I"m afraid I"m not certain about direct & indirect. But we do measure
the noise in both a residual (just the part) and the absolute (the total
noise). The residual is easier to measure but the absolute provides more
information. |
[2005-10-12 10:53:31] |
| [问：casaki] |
如果有高精度的时钟源（比如稳定度为1×10-11的微型原子钟，已经研制成功），将一个系统的所有时钟都锁定在这个源上，那么时钟的抖动是不是可以完全不用考虑了？谢谢！ |
| [答：Pascal] |
You can use PLL to lock to the atomic source. It will be just as accurate.
However, the noise (phase noise/jitter) in the output from the clock device
(AD9510) will be due to the PLL/VCO/AD9510. The PLL loop filter design
is important. However, the main source of jitter will be the broadband
phase noise of the VCO. The clock distribution IC (AD9510) will have some
broadband additive jitter, about 215 fs. This total jitter will be the
root sum of the squares of all of the sources of jitter. |
[2005-10-12 10:54:41] |
| [问：qizhi_liu] |
请问，如我们要实现一个从DC-10MHz左右模拟输入信号的高速数据采集，速度在25MSPS以上，要求精度至少在13位以上。请推荐驱动放大器、ADC芯片和采样时钟的性能及芯片。谢谢！ |
| [答：Eagle] |
我们推荐AD6654，集成14位ADC与数字下变频，不需要出口许可证。运放可用AD8351差分驱动器。时钟芯片可用AD9510或AD9511。
AD6644和AD9244是14位高速ADC，但需要出口许可证。
如果IQ采样，建议AD8347和12位双ADC AD9238。或者AD9863（集成ADC与DAC）。 |
[2005-10-12 10:55:02] |
| [问：moroseboy] |
对于时钟的抖动,你们通过什么来解决?从那方面来解决?硬件?软件? |
| [答：Mariah] |
For high performance system, we recommend you to used low jitter clock
source and treat the clock signal as analog signal in your design. |
[2005-10-12 10:56:42] |
| [问：sunzhanghong] |
ADI软件主要适合 那些场合，有些什么特除要求吗？ |
| [答：Eagle] |
Are you mean software for Eval and Simulation? Most Eval software can
run at any Window version, but need Eval board together. If Simulation
software, then it can run in any window or run on line. |
[2005-10-12 10:56:45] |
| [问：wangxiaobing] |
抖动现象是否由其他寄生频率干扰产生?我做过测试，用频普仪发现抖动时存在该频率的高次泛音。 |
| [答：Ted] |
When there are harmonics in the output spectrum, this usually means
the output is not a pure sinewave. If your VCO generates a square wave
output, it will produce harmonics in your output spectrum. But if your
VCO is supposed to be a sinewave output, check to make certain that you
are not overdriving any inputs you send the VCO frequency to. Clamping
the VCO output will also cause harmonics. |
[2005-10-12 10:57:05] |
| [问：shmm2002] |
AD9510的输出时钟抖动是否与输入有关？其输出受到输入的限制？ |
| [答：Wenshuai] |
Yes. The quality of the input clock will be one part of the total jitter.
All the jitter we give in the datasheet is the additive jitter. And you
can find this from the slides we gave just now. |
[2005-10-12 10:57:35] |
| [问：zbrxr] |
详细介绍与其他同类产品的异同及优势！ |
| [答：Ted] |
One of the biggest advantages to our clock distribution chip is that
each of the clock output channels have their own independent divider and
buffer. This reduces the coupling from one channel to another. Many of
our competitors use one divider chain and then tap off of different points.
This causes a lot of coupling. |
[2005-10-12 10:58:50] |
| [问：lpi318lpi318] |
当前，时钟稳定度测量常用方法是什么？
高精度的测量 方法能够区分同型号的时钟？
谢谢 |
| [答：Mariah] |
From today"s presentation, you can find the method of calculating the
jitter from the phase noise.
As to your second question, would you please make it more clearly? |
[2005-10-12 10:59:25] |
| [问：qawhjb] |
为减少抖动，请问设计的时候需考虑哪些因素呢 |
| [答：Eagle] |
First All, you need a good clock source. VXCO.
Then, good clock IC shuch as AD9510.
PCB layout is very important for get good performance. Use differential
lines always helpful. Seperate power supply for Clock IC, for ADC analog
circuit, ADC digital logic will be very helpful, and, with good decoupling
at VCC pin. Component placement and Sheilding will also helpful. To be
simple, treat a 100M clock line as an 1GHz analog signal line. |
[2005-10-12 11:00:19] |
| [问：encaon] |
时钟的抖动和压控振荡器(VCO)的相位噪音有何关系?是正比关系吗? |
| [答：Pascal] |
Yes. The jitter is related to the broad band phase noise of the VCO.
The jitter is proportional to the integrated power in the phase noise
sideband (SSB). This should be integrated over the bandwidth (frequency
offset from clock frequency) which is of interest or effective in the
particular situation. |
[2005-10-12 11:02:11] |
| [问：qawhjb] |
如何仿真时钟的抖动呢 |
| [答：Wenshuai] |
Please use our free tools ADISimCLK in our website http://www.analog.com/en/content
/0,2886,0%255F%255F72006,00.html |
[2005-10-12 11:03:20] |
| [问：encaon] |
要实现低抖动时钟,有那些应用的解决方案? |
| [答：Mariah] |
You can use PLL as the low jitter clock. Also we recommend you to use
our clock series products, for example AD9510. |
[2005-10-12 11:04:40] |
| [问：encaon] |
时钟的抖动对ADC的影响有多大?影响ADC的噪音有那些因素? |
| [答：Mariah] |
I can recommend you two good applications where you can find the effect
of the clock to ADC. AN501 and AN756. You can download them from the website. |
[2005-10-12 11:06:29] |
| [问：jixnjie] |
EMI和时钟的抖动之间有没有直接可以量化的关系？如果有，那么怎样才能在消除或者减小时钟抖动前提下，有效控制电路元器件之间的相互干扰？ |
| [答：Pascal] |
No. There is no relationship between the EMI and the jitter with the
relatively small phase variations involved with high quality, low noise
oscillators or frequency sources. Of course, jitter/phase noise tends
to spread power into a wide band of frequencies and away from the fundamental.
However, for low phase noise clock sources this is a very small effect.
Some CPU clock sources do introduce large amounts of phase noise in order
to spread the fundamental out and reduce EMI, but this is not the case
with clock sources intended as converter (ADC/DAC) sampling clocks. Large
phase noise/jitter will ruin the SNR of a converter long before it will
significantly reduce EMI. |
[2005-10-12 11:06:47] |
| [问：encaon] |
如何设计低抖动取样时钟电路?要注意那几方面的问题? |
| [答：Mariah] |
First of all, you should select a low jitter clock source and treat
your clock as analog signal in your PCB layout. |
[2005-10-12 11:07:53] |
| [问：lbgy] |
请解释说明相位噪声和时钟抖动之间的关系.如何测量相位噪声? |
| [答：Wenshuai] |
Please refer to the slides from 13 to 20, or the application note in
our website AN-756. The phase noise can be measured by spectrum analyser. |
[2005-10-12 11:08:38] |
| [问：riello] |
AD9510对输入基准时钟在精度和温漂上有何要求?采用那种时钟源较好? |
| [答：Ted] |
There is no temperature stability requirement for the AD9510. But the
temperature drift from the VCO & the reference will affect your output.
So, whatever frequency drift your system can tolerate is okay for the
AD9510. For a list of recommended VCOs and reference oscillators, please
see ADI SimCLK on our webpage at http://www.analog.com/clock |
[2005-10-12 11:09:10] |
| [问：wwsstt2001] |
请问贵公司的芯片主要是用于解决解密时的抖动问题的吗？型号有吗？ |
| [答：Mariah] |
The clock family products focus on providing low jitter clock for high
performance application. For example, high speed ADCs. The part number
is AD951x. |
[2005-10-12 11:09:18] |
| [问：97669] |
Can"t download ADIsimCLK .Try many times |
| [答：Wenshuai] |
Then please send E-mail china.support@analog.com. We can send one to
you. |
[2005-10-12 11:09:20] |
| [问：hsb_wh] |
软件无线电中，采样时钟有什么特殊要求和措施？ |
| [答：Pascal] |
Yes. The dynamic range of the ADC is limited by the phase noise/jitter
of the converter sample clock. That is why the best (low phase noise/low
jitter) clock is useful. There is a graphic in the presentation which
shows the maximum attainable SNR for a given amount of jitter RMS.
|
[2005-10-12 11:10:03] |
| [问：wwsmc] |
AD9510的开发板多少钱?在那里买? |
| [答：Mariah] |
$150. You can contact ADI qualified distributors to buy the EVB. The
contact information of these distributors can be found in our website. |
[2005-10-12 11:11:38] |
| [问：maeleton1] |
PCB的布线也回影响时钟的抖动,在PCB的布线上如何做才能得到最低的抖动? |
| [答：Eagle] |
Almost same as last question. Use differenital line, match to 50 Ohm
or charactristic. Seperate Clock line with Analog line and digital line,
use GND to seperate this lines. And, most of all, at least 4 layer PCB
with a big GND layer. We do not suggest seperated AGND and DGND for very
high speed ADC (>100MSPS) or multi-ADC. If you seperated AGDN and DGND,
it should be only applies to one ADC, and connect AGND and DGND under
ADC in GND layer. No any lines cross the AGDN&DGND sepeartion line.
Please consel ADI local FAE when before your PCB layout is almost finished. |
[2005-10-12 11:11:52] |
| [问：linwei1234] |
抖动和相位噪声的关系?亚皮秒抖动?超低相位噪声的测量方法? |
| [答：Wenshuai] |
Please refer to page 13 to 20 of the slides and AN-756. Our clock distributor
will have the jitter of less than 1ps. Please refer to AD9510 datasheet
for details. The phase noise can be measured by spectrum analyzer. |
[2005-10-12 11:12:30] |
| [问：lxh565] |
请问ad公司有无准确度优于1x10-7低抖动晶振或VCO？ |
| [答：Eagle] |
We do not have VCXO or standalone VCO, some decide such as ADF4360 has
integrated VCO. |
[2005-10-12 11:12:45] |
| [问：arrow_zh] |
在设计200MHz ADC电路中，如何选择时钟晶振，对晶振的抖动有何要求？ |
| [答：Ted] |
There are a series of mathematical relationships between the jitter
on the clock and the SNR on an ADC. Application notes AN756 and AN501
on our website: http://www.analog.com/clock describe these relationships
in detail. |
[2005-10-12 11:13:26] |
| [问：maeleton1] |
晶振的温漂造成频率漂移,为了得到满意的时钟抖动,晶振的温度补偿或温漂要达到多少才合适?有明确的关系或计算方法吗? |
| [答：Pascal] |
The temperature stability of the clock is not the same as the phase
noise performance of the clock. A crystal may be low phase noise, but
uncompensated for temperature drift. Conversely, a highly temperature
compensated crystal may have very bad phase noise performance.
Temperature drift is very slow in comparison to phase noise. It is the
phase noise which reduces the SNR performance of a converter. However,
frequency stability may be important for other reasons. |
[2005-10-12 11:13:33] |
| [问：maeleton1] |
在多时钟系统中,倍频和分频对时钟的抖动影响如何? |
| [答：Eagle] |
When double frequency, the clock jitter get worse. When divide frequency,
the clock jitter get improved. |
[2005-10-12 11:13:34] |
| [问：shu_chen] |
请问贵公司ADC的指标,是不是都是基于一个低抖动采样时钟给出的,是不是都是通过时钟分配芯片给出的时钟。 |
| [答：Wenshuai] |
The performance of ADC will be based on low jitter clock. The ADC test
method can be found from our converter book. Or you can conttact china.support@analog.com
to get the article. When test ADC, the clock distributor is not a must. |
[2005-10-12 11:14:18] |
| [问：riello] |
ADIsimCLK是否只适用ADI的器件? |
| [答：Mariah] |
Yes. |
[2005-10-12 11:14:31] |
| [问：dongyu_sun] |
能否简单描述产生抖动的主要原因 |
| [答：Ted] |
There are 4 reasons for jitter in a clock generation circuit: the noise
in the reference, the noise in the clock chip itself, the noise in the
VCO and finally the coupling of external signals into the output. |
[2005-10-12 11:14:44] |
| [问：shandong] |
通常解决防抖动的主要措施有那些?在保证稳定度的情况下,比较经济的解决措施? |
| [答：Ted] |
If you want to improve the jitter/phase noise in your clock output,
you will want to address what is the dominant noise component: the reference,
the clock chip, or the VCO. Once you know this, you can adjust your loop
bandwidth up or down to improve noise. This is because the loop filter
acts as a lowpass on the reference and chip noise, but a highpass on the
VCO noise. |
[2005-10-12 11:19:18] |
| [问：sunzhanghong] |
请问贵公司的芯片主要是用来解决解密时的抖动问题的吗？我想请问这种芯片的稳定性呢？还有贵公司在全国有没有销售网络，售后服务齐全吗？ |
| [答：Wenshuai] |
我们的产品主要是时钟发生器和时钟分配器，可以跟我们高性能的ADC/DAC/DDC/DUC以及其他公司的FPGA提供高性能的时钟。它的稳定性很好。我们在全国有可靠的代理商和我们自己的网络。您可以通过我们的网站找到我们的授权代理商，也可以通过免费电话800
810 1742获得技术支持。 |
[2005-10-12 11:19:36] |
| [问：lbgy] |
什么是抖动清除器?ADI有这样的产品吗? |
| [答：Ted] |
Many of our PLLs and clock products will perform jitter cleanup within
the loop bandwidth of the circuit. For example, the AD9510, which has
a PLL built, can clean up reference jitter when a very low loop bandwidth
is used. |
[2005-10-12 11:20:49] |
| [问：henryhuang] |
主机时钟干扰一般怎么排除 |
| [答：Wenshuai] |
You will use it in the PC system? If so, you can use good layout and
shield to get rid of it. |
[2005-10-12 11:21:00] |
| [问：97669] |
what"s the minimum input frequency for AD951X |
| [答：Mariah] |
No minimum input frequency limit. Please refer to the datasheet in detail. |
[2005-10-12 11:22:25] |
| [问：chloch2002] |
AD公司目前最好的时钟分配器是否是AD9510，其抖动的性能能达到多少？（在245.76MHz），该芯片是否不具备jiteer
cleaner的功能，一般测抖动该如何测试，我用泰克的示波器的抖动分析软件测试出来AD9510的抖动为RMS是8.5ps,是否准确？ |
| [答：Pascal] |
The AD9510 is one of the ADI family of clock ICs. They have different
features, for example number of outputs, PLL, etc. They all have similar
performance.
The AD9510 and AD9511 have an on-chip PLL (requires external VCO and loop
filter) which does jitter cleanup.
Please see the data sheets for the AD951x parts. These are available from
http://analog.com/clocks
The Tektronix scope does not have the ability to measure jitter as low
as the AD9510 is capable of achieving. We use more sensitive methods.
The additive jitter of the AD9510 LVPECL outputs is about 215 fs rms.
This jitter value is derived from an actual ADC SNR measurement.
However, on the evaluation board with the 245.76 MHz VCXO, the total jitter
achieved with the PLL, VCXO, and distribution section is somewhat higher
- but still on the order of 300 fs rms. If you really are seeing 8.5 ps
rms of jitter, then something is wrong with the PLL loop. Is it locked?
Please contact me by email if you want to pursue this further. Maybe we
can find where the problem is. |
[2005-10-12 11:23:23] |
| [问：guahuahua] |
AD9510不用PLL，直接分频的效果怎样 |
| [答：Wenshuai] |
This is one of the configuration of AD9510. The additive jitter is 250fs. |
[2005-10-12 11:25:14] |
| [问：maeleton1] |
在多时钟系统中,时钟的抖动对异步时钟和同步时钟的影响有何区别? |
| [答：Ted] |
It depends on how you are generating your asynchronous clock source.
If it is derived from the synchronous clock source, then there will be
an affect on the jitter. But if the asynchronous clock is free-running,
you might not have any affect between the synchronous clock and the asynchronous
clock. |
[2005-10-12 11:25:46] |
| [问：lbgy] |
什么欠采样系统?它的时钟和基带采样系统对相位抖动的性能有什么不同? |
| [答：Mariah] |
Under-sampling system is that the sampling clock frequency is below
the 2 times of the input clock frequency.
For under-sampling system,, the jitter of the clock is critical to the
ADC performance because the high input signal frequency. You can find
from the seminar presentation that the SNR of the ADC is determined by
both the jitter and the analog input frequency. So for high analog input
frequency, low jitter is more and more critical to get the high SNR. |
[2005-10-12 11:27:19] |
| [问：zzkeng] |
请介绍时序裕量和时钟抖动的两者关系? |
| [答：Mariah] |
What do you mean by 时序裕量? |
[2005-10-12 11:27:40] |
| [问：xsj19810419] |
高性能时钟主要用在哪里啊？ |
| [答：Mariah] |
Instrumentation
Time Jitter on clock degrades ability to make accurate measurements
Time Jitter on clock degrades image in medical equipment
Wireless Infrastructure Radios
Time Jitter on clock results in higher Bit Error Rate (BER), poor call
quality
Spurious signals on clock result in Adjacent Channel Interference (ACI),
dropped calls
Broadband Infrastructure
Phase Noise on clocks result in data errors, lower throughput |
[2005-10-12 11:28:53] |
| [问：guahuahua] |
AD9510的外部数据控制只需要选择通道及此通道的分频除数就可以了吗 |
| [答：Wenshuai] |
You just need to configure the registers in AD9510. It is a easy job. |
[2005-10-12 11:29:04] |
| [问：chen-lai] |
如何获得低成本的100MHz高精密时钟？AD 有否此IC，价格？ |
| [答：Ted] |
If you already have a higher rate VCO, then our mini-divider chips (such
as the AD9514) would be the lowest cost solution. If you don"t, you would
probably want to look at using a simple PLL to upconvert a stand alone
reference, such as with the ADF4106. The price will generally vary with
how many parts you are buying, but you can generally get a good 100MHz
clock for about 25 RMB. |
[2005-10-12 11:29:34] |
| [问：shu_chen] |
请问DDC时钟是否真有必要使用低抖动时钟？我感觉没有必要啊 |
| [答：Wenshuai] |
For ADC/DAC, you must use low jitter clock. For DDC/DUC, it is mainly
digital part, the requirements to jitter will be relaxed. But, you have
to consider the syncronization between ADC/DAC. |
[2005-10-12 11:30:29] |
| [问：zzkeng] |
ADI的AD9510时钟抖动性能,和业界其它产品相比如卓联等产品,有什么优势? |
| [答：Ted] |
The jitter performance is going to depend on a mulitude of factors beyond
the clock chip, such as the noise in the reference, and the VCO. For detailed
data on how jitter free the AD9510 can be, please consult the datasheet
at http://www.analog.com/ad9510. Generally speaking, our noise performance
and functionality is better than the equivalent Zarlink products. |
[2005-10-12 11:31:56] |
| [问：sunzhanghong] |
能解释一下抖动是如何产生的吗？
用上贵公司产品时，能解决你些问题？ |
| [答：Ted] |
Jitter comes from thermal noise and current carrying effects such as
shoot-through current. Our chips are generally designed to provide multiple
clocks without interference, and provide some jitter cleanup. |
[2005-10-12 11:33:54] |
| [问：meteor_chu] |
时钟抖动有随机抖动和确定性抖动,随机抖动发生在数字信号的边沿转换期间，造成随机的区间交叉,确定性抖动由IC确定,一般来说,那种对噪音有更大的影响?两者如何测量和区分而采用不同的措施来降低? |
| [答：Pascal] |
Random jitter is caused mainly by thermal and current carrier effects
in active devices (transistors). This type of jitter is what the seminar
is about.
Deterministic jitter is caused by the interaction of related or unrelated
frequencies or processes in the system. An example of deterministic jitter
would be when 2 or more dividers at different divide ratios are operating
on a single chip and there is inadequate crosstalk performance.
Our clock ICs have very low crosstalk, and exhibit very low deterministic
jitter under most conditions. They also attain low random jitter by minimizing
noise sources at every stage.
It is hard to talk about deterministic jitter in general, because it is
very specific to a given system and environment. However, random jitter
is universal, and is unavoidable - only minimizable.
Many digital oscilloscopes offer the ability to measure determistic jitter.
Random jitter below 1 ps rms is very hard to measure directly. We use
an indirect and very sensitive method to measure very low random jitter.
We derive a jitter value from an ADC SNR measurement. |
[2005-10-12 11:36:16] |
| [问：meteor_chu] |
请介绍抖动和漂移抖动的区别和相互关系? |
| [答：Ted] |
The temperature drift has nothing to do with the phase noise. The temperature
drift causes an error in the average value, not the noise around the signal. |
[2005-10-12 11:37:35] |
| [问：wenye] |
刚才的powerpoint中给出了通过jitter值计算SNR的方法，其中的信号频率是输入模拟信号的频率还是ADC的时钟频率？若是模拟信号频率，则SNR是否与ADC时钟频率相关？ |
| [答：Mariah] |
The frequency refers to the ADC input signal frequency, not the sampling
clock frequency. Please see our application note AN501 and AN756. |
[2005-10-12 11:37:44] |
| [问：guahuahua] |
AD9510的接口是IIC接口吗？还是其他的什么接口 |
| [答：Mariah] |
No. The AD9510 serial control port is compatible with most synchronous
transfer formats, including both the Motorola SPI and Intel SSR protocol.
For details, please refer to the datasheet. |
[2005-10-12 11:40:23] |
| [问：meteor_chu] |
如何评估时钟抖动对系统性能的影响?如何才能达到性能与成本的折衷方案? |
| [答：Ted] |
Evaluating the peformance depends on what you intend to use the clock
for. For an ADC, the noise in the clock will cause an error in SNR. In
a DAC, it will cause phase noise in the output. In terms of evaluating
performance versus cost, this is generally a decision that you need to
make based on your system requirements for clock noise as well as the
business details of the application. |
[2005-10-12 11:41:00] |
| [问：guahuahua] |
请问AD9510内部是一个EEPROM吗？他可以配置多少次？还是无限制次数的写进数据？是不是每次上电需要重新配置寄存器 |
| [答：Mariah] |
No EEPROM. You need to set it every time power on. |
[2005-10-12 11:43:10] |
| [问：riello] |
ADI有没有抖动测试工具套件?性能和价格如何? |
| [答：Ted] |
We do not have a direct measurement tool, but we do perform measurements
here, by measuring the phase noise and the achieved SNR in a high resolution
ADC. We do offer a simulation package that will help you estimate what
the jitter of your clock will be, ADI SimCLK: http://www.analog.com/clock. |
[2005-10-12 11:43:18] |
| [问：zzkeng] |
系统中的同步模块设计很重要,专家有什么建议,以避免信号的恶化? |
| [答：Pascal] |
The AD951X clock ICs have a method to synchronize the clock outputs.
All outputs can be synchronized with a SYNC signal. These ICs also have
phase offsets which can be selected for coarse delay adjustment (depending
on the divide-by value). Some outputs also have analog fine delay adjustments
which allow for synchronizing data with FPGA and ASIC devices. |
[2005-10-12 11:43:23] |
| [问：dtlzk] |
请问AD9510现在市场价格是多少? |
| [答：Mariah] |
$11.95 |
[2005-10-12 11:44:44] |
| [问：luogongqiang] |
如何直接测量时钟的抖动? |
| [答：Ted] |
The best way to measure the clock jitter is to actually measure the
phase noise and then integrate the phase noise over the bandwidth of interest
(such as 10KHz to 1MHz). This will yield a total phase error, which based
on the frequency of the carrier, you can convert back to a time measurement. |
[2005-10-12 11:45:22] |
| [问：luogongqiang] |
如何产生可变采样时钟?采用它能否得到低噪音的ADC性能? |
| [答：Mariah] |
AD9510 has internal divider from 1～32. |
[2005-10-12 11:45:40] |
| [问：huazheng] |
仿真调试软件可以发给我吗? |
| [答：Wenshuai] |
You can download it from our website free: http://www.analog.com/en/content
/0,2886,0%255F%255F72006,00.html
If you have any problem, feel free to contact with china.support@analog.com
or 800 810 1742 |
[2005-10-12 11:45:49] |
| [问：meteor_chu] |
相位噪声与抖动之间存在直接的关系,能否详细介绍这一关系? |
| [答：Mariah] |
They are the same phenomenon in time domain and frequency domain. You
can find the relationship and calculation between these two parameters
in the presentation. |
[2005-10-12 11:46:57] |
| [问：riello] |
ADIsimCLK工具模拟元器件的相位噪声和抖动,它的实测结果如何?有数据说明吗? |
| [答：Ted] |
All of the data within ADI SimCLK comes from actual mesaured data. The
phase noise floor has been proven to agree within 2dB at a 160dB phase
noise floor. We do have data that we measured to make the ADI SimCLK tool,
but we cannot make it available. |
[2005-10-12 11:47:11] |
| [问：qawhjb] |
为减少抖动，请问设计的时候需考虑哪些因素呢 |
| [答：Ted] |
To reduce the jitter, first look at what is causing the majority of
the jitter: the reference or the VCO. Then, you can move the loop bandwidth
up or down, because the loop filter acts like a high pass filter on the
VCO noise (a higher corner frequency removes more VCO noise) but it acts
like a low pass filter on the reference noise (a lower corner frequency
removes more VCO noise). |
[2005-10-12 11:48:47] |
| [问：arrow_zh] |
请问晶振的稳定性与AD变换的精度的关系？ |
| [答：Ted] |
The stability of the clock can affect ADC resolution. Your ADC will
employ FFT and windowing algorithms that assume a certain clock rate.
If you do not match it, it will introduce errors in your FFT data coming
out of the ADC. |
[2005-10-12 11:50:13] |
| [问：encaon] |
采样时钟的抖动对ADC的信噪比有多大? |
| [答：Eagle] |
SNR=SNR0-20Log(2*Pi*Fin*Tj).
Where Fin is input frequency, Tj is clock RMS jitter. For example, if
use a Tj=10ps clock to sample a 100MHz signal, the SNR will be less than
50dB. |
[2005-10-12 11:50:20] |
| [问：wenye] |
请问，抖动是否与时钟信号边沿的变化速率有关？ 从EMC设计的角度来讲，是否边沿速度高的信号比边沿变化速度低的信号更容易导致EMI问题？如果是，如何解决？ |
| [答：Pascal] |
Assume a clock signal with no jitter, or very low jitter. If the clock
receiver (the device being driven) is noiseless, the slew rate does not
matter. However, all real receiver circuits have some noise, so higher
slew rate clock signals tend to improve jitter performance.
Of course, higher slew rates worsen EMI. The best way to lessen EMI with
high slew rate clock signals is to use only differential signalling (LVPECL
or LVDS) with coupled differential transmission lines connecting the clock
source and receiver. Buried stripline transmission lines can greatly reduce
EMI. |
[2005-10-12 11:50:51] |
| [问：dtlzk] |
AD9510价格如何，它比AD1674在哪方面优越 |
| [答：Eagle] |
AD9510 is Clock IC, list price can be find in www.analog.com, or call
our distributors. AD1674 is an 12bit ADC, we suggest you use AD7328 for
new design(8 input channel, 12bit ADC), or use AD7321 if no many channel
needed. |
[2005-10-12 11:51:45] |
| [问：guahuahua] |
AD9512市场价是多少 |
| [答：Mariah] |
$8.95 |
[2005-10-12 11:52:55] |
| [问：maeleton1] |
能否介绍时钟频率和容许的时钟抖动的关系?比如500MHz频率,最大的抖动为多少? |
| [答：Eagle] |
Same as last question. SNR=SNR0-20log(2*PI*fin*Tj)
An example of the stringent requirements on the sampling clock can be
seen by assuming a 100MHz fullscale IF input signal. Assume that an SNR
equivalent to 14-bits is desired, the total jitter must be between 50fs
and 100ps. |
[2005-10-12 11:53:04] |
| [问：zhangfranz] |
请问：对时钟要求，10ms时间内准确度满足5E-8，如何换算到秒稳？ |
| [答：Ted] |
How long it will take your clock to settle depends on your loop filter.
ADI SimCLK can predict the settling time for your clock design based on
the loop filter you choose. You can find it at http://www.analog.com/clock. |
[2005-10-12 11:53:13] |
| [问：guahuahua] |
想请问一下，AD9510必须外接VCO吗？
AD9510与AD9511内部结构完全一样吗？ |
| [答：Pascal] |
The AD9510 distribution section can be used without the PLL. The PLL
can be turned off. The same is true of the AD9511. The AD9512 has no PLL.
The AD9511 is the same as the AD9510 internally, only with fewer outputs
and a smaller package. |
[2005-10-12 11:53:22] |
| [问：dtlzk] |
麻烦你们发一个调试软件给我,我这边下不了,谢谢!dtlzk0103@163.com |
| [答：Wenshuai] |
Please send this request to china.support@analog.com |
[2005-10-12 11:54:29] |
| [问：guahuahua] |
现在可以索取AD9510、AD9512的样片了吗？ |
| [答：Wenshuai] |
Yes. You can go to our website www.analog.com to get them. |
[2005-10-12 11:54:50] |
| [问：riello] |
信号抖动是串行器件(SERDES)设计师在兼容性问题方面面临的最大困难之一,如何解决这一问题和测试它的抖动包络? |
| [答：Ted] |
When we want to measure the jitter distribution density, we generally
use an oscilloscope that takes this measurement directly. |
[2005-10-12 11:56:41] |
| [问：zzkeng] |
屏幕抖动和画面抖动和时钟抖动有什么关系? |
| [答：Eagle] |
屏幕抖动是隔行扫描的结果。
画面抖动多是因为同步没有锁定。
时钟抖动会导致图像模糊。 |
[2005-10-12 11:57:39] |
| [问：riello] |
电源中的波纹对时钟的抖动有多大影响?要得到超低抖动时钟,对电源有和要求? |
| [答：Pascal] |
The ADI clock ICs have very good power supply isolation. The power supply
should be as low noise as possible, and suitable bypass capacitors should
be used on the PC board.
With reasonable bypassing techniques and power supplies we have had no
problems at all related to power supply noise. The IC design is very robust
with respect to PS noise, in our experience. |
[2005-10-12 11:57:41] |
| [问：xsl163] |
如何抑制抖动？ |
| [答：Pascal] |
First, identify the source of the noise which is causing the jitter.
Is the source noisy (jittery)? The PLL can be used to clean up a jittery
source.
Pay attention to slew rates and signal levels. Use differential LVPECL
or LVDS where possible.
If you have more specific questions, please contact me by email. |
[2005-10-12 12:00:39] |
| [问：zzkeng] |
什么是零延时缓冲器?采用什么办法来达到零延时? |
| [答：Eagle] |
Zero delay mean no delay of input clock and output clock. My personal
understand is that output clock edge is aline with output clock edge(exact
the same if use 2 tone Oscilloscope).
AD9510 has delay adjust, about 1.5ns. |
[2005-10-12 12:01:08] |
| [问：lbgy] |
时钟抖动是高速设计中普遍面临的问题,ADI有那些产品可提供最低的抖动和抗噪性能? |
| [答：Eagle] |
AD9510, Phase locked loop (PLL) Core Reference
input frequencies to 250 MHz Programmable dual-modulus
prescaler Programmable charge pump (CP) current
Separate CP supply (VCP) extends tuning range
Two 1.6 GHz, differential clock inputs
8 programmable dividers, 1 to 32, all integers
Phase select for output-to-output coarse delay adjust, Four independent
1.2 GHz LVPECL outputs Additive output jitter ,
225 fs RMS
Four independent 800 MHz/250 MHz LVDS/CMOS outputs, Additive output jitter,
275 fs RMS, Fine delay adjust on 2 outputs, 5-bit delay words Serial control
port Space-saving 64-lead LFCSP
AD9511, AD9512, AD9513, AD9514, AD9515, similar
AD9540 Generation PLL Core +1.8 655 1 655 CML,
PECL-compliant 0.7
total Serial, Pin Select 48-LFCSP 9.95 |
[2005-10-12 12:04:39] |
| [问：guahuahua] |
如果我不用PLL是不是选用AD9512更好，现在AD9512已经生产了吗？AD9512是不是比AD9510配置要简单一些 |
| [答：Eagle] |
Yes. AD9510/11/12 are all released. Yes, simple. Thanks! |
[2005-10-12 12:05:50] |
| [主持人：ChinaECNet] |
恭喜您， 南京洛普股份有限公司的pimingrong经过电脑抽奖您在本次座谈中获得一部MP3播放器。请网名为pimingrong的用户与中电网联系(8610-82888222-7008
或 lilin@chinaecnet.com)。 |
[2005-10-12 12:08:53] |
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