求助高手
我在使用使用ISE7.01i编写Verilog程序时遇到下面提示的WARNING，我始终无法找到出错的原因，我使用的FPGA的型号是XC2S50和XC18V01。错误可能是出现在顶层模块，但是我找不出来啊！急人啊！
`timescale 1ns / 1ns
module system_controller(reset_n,clk_100MHz,col,row,lcm_rs,lcm_rw,lcm_e,lcm_db,lcm_rst,lcm_psb);
input reset_n; //reset the whole system
input clk_100MHz; //input the clock
output[3:0] col; //column
input[3:0] row; //row
output lcm_rs; //select register 0:instrucion register 1:data register
output lcm_rw; //read/write control
output lcm_e; //read/write data start
inout[7:0] lcm_db; //data bus
output lcm_rst; //LCD reset
output lcm_psb; //select transmit mode 0:serial 1:paralle
wire[4:0] CODE;
wire PADDOWN;
wire[3:0] col;
wire[3:0] row;
wire S_Row;
wire lcm_rs;
wire lcm_rw;
wire lcm_e;
wire[7:0] lcm_db;
wire lcm_rst;
wire lcm_psb;
////////////////middle variable//////////////////////////////////////////
wire LOAD_RANGE;
wire LOAD_ANGLE;
wire START_SEND_DATA;
wire SHOW_RANGE;
wire SHOW_ANGLE;
wire SHOW_Y_N;
wire SHOW_SENDING_DATA;
/////////////////////////////////////////////////////////////////////////
reg[3:0] frequency_div_counter_1;//the counter of divided frequency
reg clk_5MHz;
/////////////// generate 5MHz////////////////////////////////////////////
always@(negedge reset_n or posedge clk_100MHz)
begin
if(reset_n==0)
begin
frequency_div_counter_1<=0;
clk_5MHz<=1'b1;
end
else
begin
if(frequency_div_counter_1==9)
begin
frequency_div_counter_1<=0;
clk_5MHz<=~clk_5MHz;
end
else
frequency_div_counter_1<=frequency_div_counter_1+1;
end
end
Hex_Keypad_Grayhill_072 U1(.Code(CODE),.Col(col),.Valid(PADDOWN),.Row(row),.S_Row(S_Row),.clock(clk_5MHz),.reset(reset_n));
Synchronizer U0(.S_Row(S_Row),.Row(row),.clock(clk_5MHz),.reset(reset_n));
calculator U2(.SHIFT_CLK(PADDOWN),.RESET(reset_n),.KEY(CODE),.CLK_100MHz(clk_100MHz),.OPT_CLK(clk_5MHz),.LOAD_RANGE(LOAD_RANGE),
.LOAD_ANGLE(LOAD_ANGLE),.START_SEND_DATA(START_SEND_DATA));
LCM_12864ZK_PHY U3(.LCM_RS(lcm_rs),.LCM_RW(lcm_rw),.LCM_E(lcm_e),.LCM_DB(lcm_db),.LCM_RST(lcm_rst),.LCM_PSB(lcm_psb),.reset_n(reset_n),
.clk_5MHz(clk_5MHz),.SHIFT_CLK(PADDOWN),.KEY(CODE),.SHOW_RANGE(SHOW_RANGE),.SHOW_ANGLE(SHOW_ANGLE),.SHOW_Y_N(SHOW_Y_N),.SHOW_SENDING_DATA(SHOW_SENDING_DATA));
center_controller U4(.CLK(clk_5MHz),.RESET(reset_n),.CODE(CODE),.VALID(PADDOWN),.LOAD_NEW_RANGE(LOAD_RANGE),.LOAD_NEW_ANGLE(SHOW_ANGEL),
.SHOW_RANGE(SHOW_RANGE),.SHOW_ANGLE(SHOW_ANGLE),.SHOW_Y_N(SHOW_Y_N),.SHOW_SENDING_DATA(SHOW_SENDING_DATA),.START_SEND_DATA(START_SEND_DATA));
endmodule
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:524 - All outputs of the instance of the block are unconnected in block .
This instance will be removed from the design along with all underlying logic
上述的信号是连接模块之间的 wire 型变量，非常的关键，结果综合的时候把它们都去掉了，所以下载到片子里无法正常工作。
我所编写的程序主要实现键盘显示功能
top_system.v //顶层模块
center_controller_se.v//主控制模块
display.v//显示模块
calculator.v//计算模块
hex16key.v//键盘扫描模块
我将所有的程序利用附件发给你们，能帮我看下错误出现在那里么，我是一个初学者，谢谢了！
http://bbs.chinaecnet.com/uploadImages/zhenghe2.rar |
